A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

Brandolini, M.; Shin, Young Jae; Raviprakash, K.; Wang, Tao; Wu, Rong; Geddada, Hemasundar Mohan; Ko, Yen-Jen; Ding, Yen; Huang, Chun‐Sheng; Shih, Wei-Ta; Hsieh, Ming-Hung; Chou, Acer; Li, Tianwei; Shrivastava, Ayaskant; Chen, Dominique Yi-Chun; Hung, Bryan Juo-Jung; Cusmai, G.; Wu, Jiangfeng; Zhang, Mo Maggie; Yao, Yuan; Unruh, Greg; Venes, Ardie; Huang, Hung Sen; Chen, Chunying

doi:10.1109/jssc.2015.2464684

Cited by 63 publications

(23 citation statements)

References 12 publications

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“…To achieve a better balance between performance and power consumption, multiple power supplies design has been used in high-speed ADCs [29,30,31]. However, these methods will result in complex power plans and consuming more power structurally.…”

Section: Improved Supply Voltage Domain Arrangementmentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

IEICE Electron. Express

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In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.

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Section: Improved Supply Voltage Domain Arrangementmentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

IEICE Electron. Express

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show abstract

“…The traditional pipelined structure has a speed merit, but the multiple amplifiers consume much power. Recently, pipelined-SAR structure has obtained much attention because it combines both the merits of pipelines and SAR ADCs [5][6][7][8][9][10][11][12][13][14][15][16][17]. As in traditional pipelined ADCs, two SAR ADCs connected by a residue amplifier (RA) can work concurrently.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

2020

Electronics

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A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

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“…However, the performance bottleneck in a direct sampling receiver is the RF-ADC. Previous studies have proven that the direct sampling RF-ADCs are required to have both high resolution (>10-bit) and fast conversion speed (>1GSps) [5][6][7][8]. Particularly, 3GSps 12-bit pipelined ADC has become a good choice due to its economy and practicality for the 5G communication.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, ph0~ph3 are not directly used as the sampling clocks. The master clock sampling is a widely used technique [7,27] to reduce the time skew. CK MC is the master clock that has a sufficiently low clock jitter to drive each clock block on the chip.…”

Section: Introductionmentioning

confidence: 99%

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Guo

Luan

et al. 2019

Electronics

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This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

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A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

Cited by 63 publications

References 12 publications

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

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