A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Abstract

In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.