This paper studies the integration of data compression into block devices built upon non-volatile memory (NVM). Although byteaddressable NVM-based main memory systems received most attention from the research community, industry chose to first commercialize NVM-based block devices, at least partly because block devices can much better mitigate non-ideal NVM characteristics (e.g., random bit errors, wear-out, and defects). It is very likely that NVMbased memory and block devices will co-exist in future computing systems, complementing to DRAM and flash memory. Compared with their flash-based counterparts, NVM-based block devices have shorter read latency but suffer from higher cost. Although data compression can reduce storage cost, conventional wisdom suggests that data compression inevitably degrades the access latency. Hence one may intuitively conclude that NVM-based block devices with built-in data compression must trade latency for bit cost. This paper shows that such an intuitive conclusion is not necessarily true. In particular, this paper presents a set of architectural design techniques that can reduce the read latency of NVM-based block devices with built-in data compression. Simulation results show that, compared with NVM-based block devices without built-in data compression, we can significantly reduce the read latency (e.g., by even more than 90%) without compromising the capability of tolerating non-ideal NVM characteristics.
In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.
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