A 5–8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization

Kim, Sung-Geun; Kim, Tongsung; Kwon, Do Young; Choi, Woo-Young

doi:10.1109/asscc.2016.7844182

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Figure 2 shows several previous FFE implementations of the voltage-mode driver [15], [16]. In the conventional FFE implementation [15], the data, D[n], and the 1-unit interval (UI) delayed inversion data, Db[n-1], are used, making the short current path from VDD to VSS during transmission of the non-transition data (Figure 2(a)); this considerably increases the overall power consumption.…”

Section: A Related Workmentioning

confidence: 99%

“…In the conventional FFE implementation [15], the data, D[n], and the 1-unit interval (UI) delayed inversion data, Db[n-1], are used, making the short current path from VDD to VSS during transmission of the non-transition data (Figure 2(a)); this considerably increases the overall power consumption. The FFE which uses a toggling serialization [16], as shown in Figure 2(b), can implement a pre-emphasis and remove the short current path. However, it needs a boosting current to implement FFE, which does not improve the overall current consumption.…”

Section: A Related Workmentioning

confidence: 99%

“…However, it is difficult to control the FFE strength finely and linearly due to the driver segmentation method, and its current-mode LVDS scheme consumes large power. A voltage-mode driver with 2-tap FFE using boosting current [16] can have good impedance matching characteristics even when nontransition data are transmitted; however, this voltage-mode structure cannot achieve independent controllability of output characteristics with a single design, and Vds variation changes the boosting current, thus making the linear FFE control difficult.…”

Section: H Comparison With Other Designs Using Ffementioning

confidence: 99%

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Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

2022

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Herein, the analog-based, 2-tap feed-forward equalization (FFE) voltage-mode transmitter using dual supply/ground voltage regulation is presented. In an FFE data modulator, the data are divided into transition and non-transition segments, and are transmitted to the main-and post-tap drivers. By using dual voltage regulation, flexible FFE strength adjustment is possible without process dependency, and the shortcurrent path is eliminated, thus improving the overall energy efficiency. Furthermore, this structure with independent impedance calibration loops has good on-resistance and return loss characteristics, thereby securing signal integrity. In addition, by regulating the supply/ground voltages, the output swing and common-mode voltage can be adjusted independently. Therefore, our transmitter can serve multiple standards and channel environments with a single design. To verify the effectiveness of our method, we designed a prototype of the source-synchronous transmitter in a 65 nm CMOS process, and its performance was compared with that of a conventional FFE design. The simulation results show that the proposed design has better on-resistance, return loss, and FFE controllability, and it has an energy efficiency of 2.23 pJ/bit at 20 Gb/s.

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Section: A Related Workmentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

Section: H Comparison With Other Designs Using Ffementioning

confidence: 99%

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Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

2022

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“…Unfortunately, this additional complexity results in increased power consumption and area costs. So that the maximum equalization capability must be considered carefully to achieve optimum power efficiency [16,17,18].…”

Section: Introductionmentioning

confidence: 99%

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Bai

Zhao

Zuo

et al. 2019

IEICE Electron. Express

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This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed transmitter consists of a novel hybrid 20:2 multiplexer followed by a three-tap feed-forward equalizer (FFE) and a shunt path SST driver. In addition, a high-precision impedance calibration circuit with slice unit replication is proposed to match the characteristic impedance of channel, whose maximum calibration error is 0.002%. Fabricated in 55-nm CMOS technology and has area of 0.024 mm 2 . Measurement results show that the transmitter achieves data rate of 8 Gbps while maintaining good performance. The transmitter has output swing of 510 mV with −6 dB post-tap equalization, and it consumes 15.1 mW under 1.2 V power supply.

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A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

Kim

Park

et al. 2021

IEEE J. Solid-State Circuits

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A 5–8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization

Cited by 5 publications

References 6 publications

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

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