A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs

Titus, W.; Kenney, J.G.

doi:10.1109/jssc.2012.2185572

Cited by 17 publications

(13 citation statements)

References 9 publications

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“…Although similar to what was shown in [3], the large frequency spacing between typical VCO bands to obtain large tuning ranges requires very large R and C values to prevent cycle slipping.…”

Section: Vco Band Switching Circuitsupporting

confidence: 52%

“…In [1]- [2], the secondary tuning is implemented using a varactor but requires large capacitors to keep the secondary feedback bandwidth low for stability and to reduce the phase noise. In [3]- [5], the secondary tuning is done with switched arrays of small varactors or capacitors, which allows for digital filtering instead. However, the large number of elements increases parasitic capacitance, and the implementation in [4] requires a digital-to-analog converter (DAC) with a switch matrix.…”

Section: Introductionmentioning

confidence: 99%

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A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

Lam

Riley

Filiol

et al. 2015

IEEE Trans. Circuits Syst. II

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This paper presents a 0.009 to 1.4 GHz frequency synthesizer that is able to compensate for changes in frequency tuning range due to temperature variations by switching VCO bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a sub-threshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm 2 of silicon area and has minimal power consumption and minimal effects on the synthesizer's phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18 µm SiGe BiCMOS process and achieves 365 fs integrated jitter at 1.05 GHz with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.Index Terms-Analog integrated circuits, BiCMOS integrated circuits, frequency synthesizer, phase-locked loop (PLL), radio frequency integrated circuits, tunable circuits and devices, sub-threshold CMOS circuits, voltage-controlled oscillators (VCOs)

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Section: Vco Band Switching Circuitsupporting

confidence: 52%

Section: Introductionmentioning

confidence: 99%

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

Lam

Riley

Filiol

et al. 2015

IEEE Trans. Circuits Syst. II

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“…This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. Some unique features are a 4-core DCO covering an octave from 5.6-11.5GHz [1], downsampling of data rather than dividing a clock to span the more than 10 octaves of rate, a digital delay-locked loop with clock phase shifter, a FIFO cascaded with a serializer to retime the data on a clean clock, and a data sampler that can oversample the receive eye by a factor of 4 for phase and frequency detection. Additional features beyond the scope of this paper are a user selectable input of either (a) limiting amplifier with 10mV sensitivity and loss-of-signal detector, (b) an adaptive equalizer with up to 12dB of boost at 5.6GHz, or (c) bypass mode.…”

Section: Introductionmentioning

confidence: 99%

“…In [1], [2] and [3], the DLL implements a phase shift on data. For frequencies above the jitter transfer bandwidth of the CDR and below the DLL bandwidth, the phase shifter absorbs most of the jitter on the data to provide an input with reduced jitter to the sampling flip flops in the phase detector.…”

Section: Introductionmentioning

confidence: 99%

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery

Kenney

Chen

DeVito

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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“…Finally, the proposed CDR has the capability to combine with a PLL to decouple jitter transfer and JTOL bandwidths to achieve superior jitter performance [1], [14]. Compared with the architectures in [1] and [14], the proposed PI can be used to adjust the clock phase instead of delaying the data [7], [15]. It is a better solution for high-speed applications, as the data phase shifter that covers a wide range of tunable delay is power-consuming and introduces intersymbol interference distortion.…”

mentioning

confidence: 99%

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

Huang

et al. 2024

IEEE Trans. VLSI Syst.

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An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme, which enables continuous data rate support. The digital architecture not only eliminates the large filtering capacitor, but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm 2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. Measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the SONET OC-192 jitter tolerance mask at least by 0.2 UI at high frequencies (4-100 MHz), with 2 31 − 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10 −12 .Index Terms-All-digital, clock and data recovery (CDR), dithering jitter, high linearity, jitter tolerance (JTOL), low-pass filter (LPF), multimode phase detection, phase interpolator (PI), wideband.

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A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs

Cited by 17 publications

References 9 publications

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

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