Proceedings of the IEEE 2014 Custom Integrated Circuits Conference 2014
DOI: 10.1109/cicc.2014.6946023
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A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery

Abstract: A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2X2mm 2 , and is implemented in a 24-pin LFCSP.

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Cited by 5 publications
(1 citation statement)
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“…To cover the input data format from a few gigabits per second to tens of gigabits per second, the “analog” receiver necessitates a clock and data recovery (CDR) circuit with a very wide frequency capture capability 4 . Previous work 5 employs a low‐noise crystal as a reference clock, which increases the overall cost and the design complexity. Reference‐less CDR mainly targets applications that are not feasible to use an external crystal 6 .…”
Section: Introductionmentioning
confidence: 99%
“…To cover the input data format from a few gigabits per second to tens of gigabits per second, the “analog” receiver necessitates a clock and data recovery (CDR) circuit with a very wide frequency capture capability 4 . Previous work 5 employs a low‐noise crystal as a reference clock, which increases the overall cost and the design complexity. Reference‐less CDR mainly targets applications that are not feasible to use an external crystal 6 .…”
Section: Introductionmentioning
confidence: 99%