A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

Ding, Ming; Harpe, Pieter; Liu, Yao‐Hong; Barankin, Benjamin; Philips, Kathleen; Groot, Harmke de

doi:10.1109/jssc.2016.2609849

Cited by 72 publications

(30 citation statements)

References 20 publications

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“…4(a) shows the histogram of a Monte Carlo simulation (100 instances) of such time difference in a fast-p corner (lower sensitivity to ∆C var variations). As it can be seen, the time difference is positive, as required by (7), and amounts 0.275ns (3-σ).…”

Section: Designing Vcdl For Offset Cancellationmentioning

confidence: 84%

“…IV for m = 3 (each VCDL comprises 7 digitally controlled delay cells). The comparator was designed to have a correction step of approximately 1.4mV pp to satisfy (7). With this structure, post-layout simulations show that the offset range, which can be canceled up by the OCTD comparator alone, is comprised between ±4.7 and ±5.3 LSBs, taking into account 3-σ deviations as in [1] [9].…”

Section: Methodsmentioning

confidence: 99%

“…Given the expected low temperature and voltage supply variations in the targeted applications (wearable/implanted devices work at about the body temperature and are often supplied by batteries and/or regulated with LDOs), background offset calibration techniques, as proposed in [7], [8], are not a major requirement. Instead, foreground calibration approaches suffice in typical scenarios, potentially leading to simpler circuits and smaller die area occupations.…”

Section: Introductionmentioning

confidence: 99%

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Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors

Fiorelli

Delgado‐Restituto

Rodríguez-Vázquez

2020

IEEE Trans. Circuits Syst. II

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This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10bit SAR-ADC. The design, fabricated in a 0.18µm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.

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Section: Designing Vcdl For Offset Cancellationmentioning

confidence: 84%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors

Fiorelli

Delgado‐Restituto

Rodríguez-Vázquez

2020

IEEE Trans. Circuits Syst. II

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“…The effect of calibration can be enhanced by using both add and subtract operations. The subtract operation is implemented by taking advantage of the differential structure [ 22 ]. To simplify the logic for the subtract operation and consider the layout parasitic, the size of the original DAC capacitors is reduced by 0.5 C U .…”

Section: Designmentioning

confidence: 99%

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Lee

Park

Cho

et al. 2018

Sensors

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Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

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“…Due to variations in the fabrication process, the values of the fabricated capacitors in a typical SAR ADC differ from their nominal values. Prior to the advent of digital calibration techniques, the output of such a SAR ADC had only moderate resolution, and it was necessary to choose the capacitor sizes to be sufficiently large so as to reduce the effect of mismatch [4]. However, by including capacitor mismatch calibration, this is no longer the case, and the capacitor sizes are now designed according to thermal noise considerations only, leading to faster ADCs having lower power and a smaller silicon area [4].…”

Section: Introductionmentioning

confidence: 99%

Blind SAR ADC capacitor mismatch calibration

Salib

Flanagan

Cardiff

2017

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency on the input signal's probability density function, the histogram windows are normalized with respect to their peaks. Matlab simulation results show that an ENOB within 0.12bit of the optimal is attained using the proposed algorithm. Index terms-SAR ADC, capacitor mismatch, calibration. I.

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A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

Cited by 72 publications

References 20 publications

Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors

Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Blind SAR ADC capacitor mismatch calibration

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