A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

Balan, Vishnu; Caroselli, Joe; Chern, Jenn-Gang; Chow, Chung-Kai; Dadi, Ratnakar; Desai, C.; Lü, Fang; Hsu, David; Joshi, Prachi; Kimura, Hiroshi; Liu, C.Y.; Pan, Tzuwang; Park, R.; You, Cheolwoo; Zeng, Yi Cheng; Zhang, E.; Zhong, Freeman

doi:10.1109/jssc.2005.848180

Cited by 68 publications

(32 citation statements)

References 5 publications

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“…The circuit can be found in Fig.11. The main function of this block is to retime the data and make decisions every bit period [6]. In our design, the two-stage Slicer utilizes the clock provided by CDR to sample data streams.…”

Section: Structure Of Receivermentioning

confidence: 99%

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology

Wang¹,

Wang²,

Gui³

2015

Proceedings of the 2015 4th International Conference on Computer, Mechatronics, Control and Electronic Engineering

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Abstract.A 5-Gb/s transceiver in 90nm technology has been presented in this paper. To mitigate the effects of channel loss, a 4-tap feed-forward equalizer (FFE) is included in the transmitter. Meanwhile, the receiver employs continuous-time linear equalizer (CTLE) to amplify high frequency signal. The clocks of the transmitter are supplied by Phase-Locked Loops (PLL) while clocks in the receiver are provided by clock recover circuit (CDR). To facilitate the testing, built-in pseudo-random sequence (PRBS) generator and PRBS detector are integrated in this chip. Fabricated in 90nm CMOS technology, the transceiver consumes 156mW under 1.2V supply. IntroductionWith the rapid development of wire-line communication, data rates grow exponentially over the past decades, especially in digital computing and signal processing fields. In order to meet the growing demand for high-speed data transmission, Serdes (Serializer/Deserializer) is gradually replacing the traditional parallel buses and becoming the mainstream of high-speed interface. Serdes is a kind of multiplexing technology that converts data from parallel to serial, reducing the communication channels and chip pins.In inter-chip communication over PCB or backplane, avoiding reflection and Inter-Symbol Interference (ISI) are the main challenges for robust communication. Reflection in transmission line (T-line) can be reduced by proper T-line design. But ISI stems from Low-Pass Filter (LPF) characteristics of the actual line and becomes severe as either the data rate or the length of the T-line increases. Hence, ISI compensation is critical in over 5-Gb/s data communication. Equalizers in transmitter and receiver are necessary for compensation of ISI. This paper describes the design of key elements of a 5-Gb/s transceiver. The transceiver uses fixed transmitter feed-forward equalizer (FFE) in combination with analog equalizer in the receiver for line equalization. A system design overview including a description of FFE, analog equalizer and the transceiver architecture will be given. Next, the key circuit components of the transceiver will be described in detail. These components include the FFE-based transmitter equalizer, a linear receiver analog front-end with Continuous-Time Linear Equalizer (CTLE), Limiting Amplify (LA) and Slicer.Fabricated in 90-nm CMOS technology, the transceiver dissipates 156mW from a 1.2V supply and Phase-Locked Loops (PLL) is integrated on chip in this paper.

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Section: Structure Of Receivermentioning

confidence: 99%

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology

Wang¹,

Wang²,

Gui³

2015

Proceedings of the 2015 4th International Conference on Computer, Mechatronics, Control and Electronic Engineering

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“…Another form of equalization is the decision-feedback equalization, or DFE [1][2][3][4][5], which can overcome the drawback of high-frequency noise amplification. DFE uses clean decisions of previously received symbols to remove ISI in the current symbol.…”

Section: Introductionmentioning

confidence: 99%

“…In [2], a PLL block is used to generate multiphase clocks. The RX uses the PLL clock as an initial guess for the incoming data phase and frequency.…”

Section: Introductionmentioning

confidence: 99%

“…Look-ahead DFE (LADFE) structure with only one posttap is employed in [4,5]. Although maximum data rate can be obtained with LADFE due to its smallest loop feedback delay, the hardware overhead, like in [2], may become prohibitive when a large number of taps is required for legacy backplane system. In this paper, a multi-tap half-rate DFE structure is used.…”

Section: Introductionmentioning

confidence: 99%

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A 0.18¿¿m CMOS Receiver with Decision-feedback Equalization for Backplane Applications

Kwaśniewski

Wang³

2006

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

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Abstract-Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in highspeed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling at 5-Gb/s over 34" FR4 backplane, SPECTRE simulation in 0.18-µm CMOS process has shown the design feasibility.

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“…The authors of [11] consider duobinary signaling, and use a frequencydomain fitting to determine the coefficients of a finite impulse response (FIR) linear pre-equalizer. In [12], the combination of a programmable 2-tap pre-equalizer at the transmitter and an adaptive 4-tap decision-feedback equalizer (DFE) at the receiver are investigated for NRZ signaling. In [4], a 2-tap pre-equalizer with fractional delay is optimized numerically to minimize a semi-analytically computed bit error rate (BER).…”

mentioning

confidence: 99%

Performance analysis of pre-equalized multilevel partial response schemes

Guenach

Jacobs

Kozicki

et al. 2015

2015 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)

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Abstract-In order to achieve high speed on electrical interconnects, channel attenuation at high frequencies must be dealt with by proper transceiver design. In this paper we investigate finitecomplexity MMSE pre-equalization under an average transmit power constraint, to compensate for channel distortion in the case of both full-response and precoded partial response signaling with L-PAM mapping, and consider the resulting error performance for symbol-by-symbol detection and sequence detection. For a representative electrical interconnect, we point out that the constellation size (2-PAM or 4-PAM), the type of signaling (full response or partial response), the detection method (symbol-bysymbol detection or sequence detection) and the number of preequalizer taps should be carefully selected in order to achieve satisfactory error performance at high data rates. For several scenarios, precoded duobinary 4-PAM is found to yield the best error performance for given average transmit power.

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A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

Cited by 68 publications

References 5 publications

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology

A 0.18¿¿m CMOS Receiver with Decision-feedback Equalization for Backplane Applications

Performance analysis of pre-equalized multilevel partial response schemes

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