A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology

Abstract

Abstract.A 5-Gb/s transceiver in 90nm technology has been presented in this paper. To mitigate the effects of channel loss, a 4-tap feed-forward equalizer (FFE) is included in the transmitter. Meanwhile, the receiver employs continuous-time linear equalizer (CTLE) to amplify high frequency signal. The clocks of the transmitter are supplied by Phase-Locked Loops (PLL) while clocks in the receiver are provided by clock recover circuit (CDR). To facilitate the testing, built-in pseudo-random sequence (PRBS) generator and PRBS detector are integrated in this chip. Fabricated in 90nm CMOS technology, the transceiver consumes 156mW under 1.2V supply. IntroductionWith the rapid development of wire-line communication, data rates grow exponentially over the past decades, especially in digital computing and signal processing fields. In order to meet the growing demand for high-speed data transmission, Serdes (Serializer/Deserializer) is gradually replacing the traditional parallel buses and becoming the mainstream of high-speed interface. Serdes is a kind of multiplexing technology that converts data from parallel to serial, reducing the communication channels and chip pins.In inter-chip communication over PCB or backplane, avoiding reflection and Inter-Symbol Interference (ISI) are the main challenges for robust communication. Reflection in transmission line (T-line) can be reduced by proper T-line design. But ISI stems from Low-Pass Filter (LPF) characteristics of the actual line and becomes severe as either the data rate or the length of the T-line increases. Hence, ISI compensation is critical in over 5-Gb/s data communication. Equalizers in transmitter and receiver are necessary for compensation of ISI. This paper describes the design of key elements of a 5-Gb/s transceiver. The transceiver uses fixed transmitter feed-forward equalizer (FFE) in combination with analog equalizer in the receiver for line equalization. A system design overview including a description of FFE, analog equalizer and the transceiver architecture will be given. Next, the key circuit components of the transceiver will be described in detail. These components include the FFE-based transmitter equalizer, a linear receiver analog front-end with Continuous-Time Linear Equalizer (CTLE), Limiting Amplify (LA) and Slicer.Fabricated in 90-nm CMOS technology, the transceiver dissipates 156mW from a 1.2V supply and Phase-Locked Loops (PLL) is integrated on chip in this paper.

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS

“…It is well known that DFE is only able to cancel the post-cursor ISI and leaves the pre-cursor ISI to the continuous-time linear equalizer (CTLE) and feedforward equalizer (FFE) [8]. However, CTLE and FFE cannot provide sufficient equalization as they amplify noise and cross-talk.…”