A 4.3fJ/Conversion-Step 6440μm<sup>2</sup> All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Xin, Haoming; Pelzers, Kevin; Baltus, Peter; Cantatore, Eugenio; Harpe, Pieter

doi:10.1109/vlsicircuits18222.2020.9162817

Cited by 6 publications

(6 citation statements)

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“…However, this would not only require a capacitive sensor without any leakage but would also introduce significant additional requirements to the readout electronics, which would lead to much more power being consumed in the readout electronics than would be saved from recharging the sensor capacitance. An interesting capacitive sensor interface is presented in [33], which is an intermediate solution between recharging the sensor capacitance at every reading, and a single initial charging. This solution demonstrates the best power efficiency FoM (see Table I).…”

Section: A Minimum Energy Consumption Analysis Of the Thermal Noise Limited Interfacementioning

confidence: 99%

“…As a switched capacitor feedback digital-to-analog converter (DAC) is typically used in a SAR ADC, the SAR approach can be conveniently used for capacitance sensing. By taking advantage of the great energy efficiency of the SAR approach, SAR-based capacitive sensor interfaces [6,7,33,34] also achieve excellent energy efficiency amongst other capacitive sensor interface architectures. In general, SAR-based capacitive sensor interfaces can be divided into two categories: 1) direct SAR capacitive sensor interfaces and 2) capacitive sensor interfaces, which include a capacitance to voltage front-end (CVFE) and a SAR ADC.…”

Section: B Sar-based Capacitive Sensor Interfacesmentioning

confidence: 99%

“…To reduce the energy consumption of the capacitive bridge, thus improving the FoM of the capacitive sensor interface towards the FoM of a standalone SAR ADC, [33] proposed an energy-efficient charge reuse technique. The concept of charge reuse in a capacitive bridge CVFE is shown in Fig.…”

Section: ) Capacitive Bridge Cvfe Followed By a Sar Adcmentioning

confidence: 99%

“…As a result, charge reuse over 80 consecutive measurements is achieved, which greatly reduces the bridge energy consumption. Thanks to this approach, a record low FoM of 4.3fJ/conv-step is achieved in [33].…”

Section: ) Capacitive Bridge Cvfe Followed By a Sar Adcmentioning

confidence: 99%

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Power-Efficiency Evolution of Capacitive Sensor Interfaces

et al. 2021

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Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This paper reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing ΔΣ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on ΔΣ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.

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Section: A Minimum Energy Consumption Analysis Of the Thermal Noise Limited Interfacementioning

confidence: 99%

Section: B Sar-based Capacitive Sensor Interfacesmentioning

confidence: 99%

Section: ) Capacitive Bridge Cvfe Followed By a Sar Adcmentioning

confidence: 99%

Section: ) Capacitive Bridge Cvfe Followed By a Sar Adcmentioning

confidence: 99%

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Power-Efficiency Evolution of Capacitive Sensor Interfaces

et al. 2021

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“…For this, the sensor undergoes the charge–discharge cycle for every sample, and charge sharing of the capacitor DAC occurs at every conversion step. Therefore, a method to reduce the conversion energy required per sample by reducing the conversion step or the number of samplings is used [ 53 , 54 ].…”

Section: Technical Issues Of the Capacitive Sensor Readout Systemmentioning

confidence: 99%

Readout Circuits for Capacitive Sensors

Yoo

Choi

2021

Micromachines

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The development of microelectromechanical system (MEMS) processes enables the integration of capacitive sensors into silicon integrated circuits. These sensors have been gaining considerable attention as a solution for mobile and internet of things (IoT) devices because of their low power consumption. In this study, we introduce the operating principle of representative capacitive sensors and discuss the major technical challenges, solutions, and future tasks for a capacitive readout system. The signal-to-noise ratio (SNR) is the most important performance parameter for a sensor system that measures changes in physical quantities; in addition, power consumption is another important factor because of the characteristics of mobile and IoT devices. Signal power degradation and noise, which degrade the SNR in the sensor readout system, are analyzed; circuit design approaches for degradation prevention are discussed. Further, we discuss the previous efforts and existing studies that focus on low power consumption. We present detailed circuit techniques and illustrate their effectiveness in suppressing signal power degradation and achieving lower noise levels via application to a design example of an actual MEMS microphone readout system.

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Capacitance-to-digital converter in dual-mode logic: power consumption vs conversion time trade-off

Aiello

Crovetti

2023

Analog Integr Circ Sig Process

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A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Cited by 6 publications

References 1 publication

Power-Efficiency Evolution of Capacitive Sensor Interfaces

Power-Efficiency Evolution of Capacitive Sensor Interfaces

Readout Circuits for Capacitive Sensors

Capacitance-to-digital converter in dual-mode logic: power consumption vs conversion time trade-off

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A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Cited by 6 publications

References 1 publication

Power-Efficiency Evolution of Capacitive Sensor Interfaces

Power-Efficiency Evolution of Capacitive Sensor Interfaces

Readout Circuits for Capacitive Sensors

Capacitance-to-digital converter in dual-mode logic: power consumption vs conversion time trade-off

Contact Info

Product

Resources

About

A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse