The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart.

A high-slew-rate low-power rail-to-rail buffer amplifier, which is suitable for thin film transistor liquid crystal display (TFT LCD) data driver applications, is proposed. Previous dynamic biasing approaches become ineffective as an output signal approaches VDD or VSS supplies. However, the proposed buffer amplifier with a dynamic biasing circuit enhances the slew rate throughout the entire rail-to-rail signal range. The buffer amplifier and the previous counterparts were fabricated in a 0.35 mm CMOS technology with 3.3 V supply voltage. Measurements show that the slew rate for rail-to-rail signal transition is enhanced from 0.80 V/ms of a previous counterpart to 2.75 V/ms. Introduction: Higher resolution and frame frequency are required on thin film transistor liquid crystal displays (TFT LCDs) for natural motion picture and three-dimensional displays. The frame frequency should be elevated from typically 60 to 480 Hz [1]. Consequently, the driving time for each row must be decreased inverse proportionally, and TFT LCD data drivers should be equipped with high-slew-rate buffer amplifiers to accommodate the need for decreased driving time.In addition, data drivers should have the rail-to-rail input range to cover the liquid crystal driving voltage and also have the push-pull output stage to support N-dot polarity inversion driving for high image quality and low power consumption [2]. The rail-to-rail foldedcascode class-AB amplifier in [3] is widely used to meet these requirements.Several buffer amplifiers for TFT LCD data drivers have been proposed to enhance the slew rate with minimal increase in the quiescent current [4][5][6][7]. In [4], the buffer amplifier uses comparators to sense the slewing conditions, but it does not support the push-pull operation. In [5], an additional current path is inserted, but the circuit requires a clock signal, which increases the circuit complexity and power consumption. The dynamic biasing circuits in [6] and [7] detect the slewing conditions and turn on the auxiliary current sources. The enhancement of the slew rate, however, ceases when the output voltage approaches VDD or VSS, which degrades the overall slew rate for the rail-to-rail signal swings. In this Letter, we propose a buffer amplifier for a TFT LCD data driver with a dynamic current biasing circuit that enhances the slew rate in the entire rail-to-rail signal range.

In this work, we examined the mechanical durability of island-type a-IGZO thin-film transistors (TFTs). Island TFTs were fabricated on polyimide (PI) islands and were transferred to a thermoplastic polyurethane (TPU) film. In repeated bending tests with a 1.5 mm bending radius, island TFTs showed less electrical property deterioration than TFTs on a PI film. We confirmed that the TPU, which has a lower elastic modulus compared to PI, effectively reduced the curvature of PI island even under the same bending test conditions. Furthermore, an organic passivation layer was applied on the upper part of the PI island. The 3 μm thick organic passivation layer made the TFT layer more stable against bending and elongation stress. Island TFTs with an organic passivation layer showed a change in the saturation mobility of only −2.3% and a change in the threshold voltage of −0.22 V even after 250 000 repetitive bending tests. Additionally, no change in electrical properties was observed even after 10 000 repeated stretching test cycles under 30% uniaxial elongation. Finally, we fabricated island-type logic circuits based on a-IGZO TFTs for wearable electronic applications. Using the organic passivation layer, we showed that the NMOS pseudoinverter and NAND gate also operated without significant deterioration in 100 000 repeated bending cycles and 5000 repeated stretching cycles. After applying repeated mechanical stresses, the high output voltage (V OH) and low output voltage (V OL) of the inverter only changed from 8.85 to 8.93 V and from 0.44 to 0.50 V, respectively. In NAND gates, V OH and V OL only changed slightly from 8.46 to 8.56 V and from 0.45 to 0.55 V, respectively.

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual‐rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data‐independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.

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To implement a compact-area 8-bit digital-to-analog converter (DAC) for system-on-panel (SoP) application, a panel DAC concept is proposed to apply a cyclic DAC to low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) driver circuits, which utilizes a pair of data lines as capacitors for the cyclic DAC. This means that a large part of the DAC circuit is implemented on the pixel area, thus saving the peripheral circuit area for the DAC. Another important impact of the proposed scheme is that we can eliminate the buffer amplifier to drive the capacitive data lines, because the analog voltage of the DAC is produced on the data line itself. However, the capacitances of two data lines should match with a 1% difference for the 8-bit cyclic DAC. The data line capacitance is basically parasitic and is fabricated by wet etching, so such tight matching is almost impossible. Therefore, the use of the hybrid DAC which combines a 6-bit resistor-string DAC and a 2-bit cyclic DAC is a more feasible approach, because the capacitance difference of up to 50% between the two data lines is allowed for the 2-bit cyclic DAC. The area increase in the 8-bit hybrid DAC is limited to 21% compared with that in the 6-bit resistor-string DAC, and the power consumption is about 13.3 mW for a 2-in. quarter video graphic array (qVGA) active matrix organic light emitting diode (AMOLED) panel.

We have developed Shared Column-Line Driving (SCLD) method, by which the number of data driver LSIs is reduced to a half of conventional ones without doubling the number of gate lines. This paper shows the concept and system configuration of the SCLD method which can be applied for high pixel density and low cost TFT-LCDs. . IntroductionThese days active matrix liquid crystal displays(AMLCDs) have been widely used for many applications. And its resolution is becoming higher. In other words, pixel pitch is becoming smaller. However, tape carrier package(TCP) and tape automated bonding(TAP) techniques do not satisfy the small and fine pitch characteristics for the small size and high resolution applications such as cellular phones and personal digital equipments. Therefore, there are lots of researches about package of AMLCD such as chip on glass(COG) to overcome the pitch limitation of TCP and TAP. And also, there was a research to increase the resolution of AMLCD without change of package types and bonding technologies. It was the half-column-line driving method which was proposed for reducing the power consumption and module cost, originally[1].This driving method can reduce the number of column driver LSIs by which each column line drives both pixels on its right and left sides and reduce the power consumption of column drivers in the module to a half but its panel has twice as many gate lines as those of a conventional one. These doubled gate lines decrease the aperture ratio and the rearranged of video data as zig-zag sequence increase the complexity of controller and digital data rate between frame memory and controller and also slightly increase the module cost because of double numbered gate driver.And two pixel are driven in one horizontal line time, it has not enough line time to drive the high resolution TFT-LCDs. To eliminate this problem, we propose a Shared Column-Line Driving(SCLD) method. In this paper, we describe the concept, and operation principle of the proposed pixel structure, and architectures and configurations of scan driver and data driver for implementation of the proposed SCLD method. Pixel Structure of SCLD MethodThe pixel array for the proposed SCLD method is shown in Fig. 1. The proposed SCLD method can reduce the number of column lines by half of the conventional LCD panel without increasing the number of gate lines. One column line is connected to the both side pixels on its right and left sides. Two pixel TFTs in the right side of the column line connected to N-th gate line. In the left side of the column line, one pixel TFT is connected to the N-th gate line and the other is connected to (N+1)-th gate line. And two series connected TFTs of right pixel, those gate are connected N-G1 G2 G3 G4 D1 D2 Figure 1. The pixel structure of the proposed shared columnline driving method. G2 G3 G1 1st H 2nd H a b Vdd gnd positive video range negative video range D1 Vcom Figure 2. The waveform of the scan pulse and driving sequence of the proposed SCLD method.th gate line, are reduced to one T...

There is the problem of picture quality nonuniformity due to thin film transistor (TFT) characteristic variations throughout a panel of large-area high-resolution active matrix organic light emitting diodes. The current programming method could solve this issue, but it also requires very long charging time of a data line at low gray shades. Therefore, we propose a new driving method and a pixel circuit with emission-current sensing and feedback operation in order to resolve these problems. The proposed driving method and pixel circuit successfully compensate threshold voltage and mobility variations of TFTs and overcome the data line charging problem. Simulation results show that emission current deviations of the proposed driving method are less than 1.7% with AE10:0% mobility and AE0:3 V threshold voltage variations of pixel-driving TFTs, which means the proposed driving method is applicable to large-area high-resolution applications.