Power-Efficiency Evolution of Capacitive Sensor Interfaces

Abstract

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This paper reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing ΔΣ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on ΔΣ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.

Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems

“…Here, the capacitance reading circuit generally converts the variation in capacitance into a digital signal so that information can be easily processed in a subsequent digital system. Capacitance detection has two main techniques: (1) capacitance-to-time (C-T) transformation and (2) capacitance-to-voltage (C-V) transformation [6].…”

“…Here, the capacitance reading circuit generally converts the variation in capacitance into a digital signal so that information can be easily processed in a subsequent digital system. Capacitance detection has two main techniques: (1) capacitance-to-time (C-T) transformation and (2) capacitance-tovoltage (C-V) transformation [6]. The capacitance-to-digital converter (CDC) using the C-T conversion technique is based on period modulation (PM) that converts the detected capacitance into different pulse width using oscillators [6,7].…”

“…Capacitance detection has two main techniques: (1) capacitance-to-time (C-T) transformation and (2) capacitance-tovoltage (C-V) transformation [6]. The capacitance-to-digital converter (CDC) using the C-T conversion technique is based on period modulation (PM) that converts the detected capacitance into different pulse width using oscillators [6,7]. PM-based CDCs have been widely used due to the fact of their simple and compact structure based on C-T converters (CTCs) and a comparator [7,8].…”

“…The authors of [9] proposed another type of C-T conversion, inverter chain-based fully digital CDC. This structure does not require analog blocks, which demonstrates better power efficiency and compactness at the cost of coarse resolution limited by the nonlinearity of inverter chain discharge [6].…”

Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

“…Many architectures of CDCs are demonstrated in the literature, exploiting the principles of phase/pulse modulation (PM) [ 3 , 4 , 5 , 6 , 7 ], modulation ( M) [ 8 , 9 , 10 ] and capacitive successive approximation register (CSAR) [ 11 , 12 , 13 , 14 , 15 ]. A detailed review of these techniques can be found in [ 16 ].…”