This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at VDD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.
The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations.
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