A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

Riedlinger, R.; Arnold, Ron; Biro, Larry; Bowhill, Bill; Crop, Jason; Duda, Kevin R.; Fetzer, E.; Franza, Olivier; Grutkowski, T.; Little, C.; Morganti, C.; Moyer, G.; Munch, Ashley O.; Nagarajan, Mali; Parks, Curtis H.; Poirier, C.; Repasky, B.; Roytman, E.; Singh, T.; Stefaniw, M. W.

doi:10.1109/jssc.2011.2167809

Cited by 47 publications

(17 citation statements)

References 8 publications

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“…Then, they were implemented at RTL level in Verilog-2001 (IEEE 1364) as technology-independent reusable IP-cores [1], using exactly the same optimized coding style for an equitable comparison. They are compile-time reconfigurable according to N and r. Reader is referred to [11], [19], and [12] for recoding tables used in equations (9), (10), and (13), respectively.…”

Section: Physical Implementationmentioning

confidence: 99%

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A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2013

Journal of Low Power Electronics

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Section: Physical Implementationmentioning

confidence: 99%

“…To increase the speed of the multiplier, most ancient processors employed radix-8, such as: Fchip [4], IBM S/390 [5], Alpha RISC [6], IA-32 [7] and AMDK7 [8]. While radix-16 is used only in the most recent Intel processors: 64 and IA-32 [9], and Itanium-Poulson [10].…”

mentioning

confidence: 99%

A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2013

Journal of Low Power Electronics

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“…As the wordlength becomes longer, the radix has been extended to radix-8 [4]- [6] and even radix-16 [7]. The advantage is that the PP reduction tree is shallower (faster and less power demanding) at expenses of a more complicate PP generation.…”

Section: Introductionmentioning

confidence: 99%

“…We chose radix-16 to limit the depth of the PP accumulation tree and save power. The unit was inspired by the implementation in the Intel Itanium FP-unit [7].…”

Section: Introductionmentioning

confidence: 99%

A multi-format floating-point multiplier for power-efficient operations

Nannarelli

2017

2017 30th IEEE International System-on-Chip Conference (SOCC)

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Abstract-In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, doubleprecision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved.

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“…The small number of partial products is especially favorable when implementing a pipeline multiplier. Another study [2] proposes an Itanium processor that uses four clock cycles for the pipeline multiplier. In this case, large pipeline registers are required because the Wallace (or carry-save adder) tree is divided by the pipeline registers.…”

Section: Introductionmentioning

confidence: 99%

Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

Kim

Moon

Lee

2014

IEICE Electron. Express

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In this study, we propose a radix-16 Booth multiplier using a novel weighted 2-stage Booth algorithm. Most conventional multipliers utilize radix-4 Booth encoding because a higher radix increases encoder complexity. To resolve this problem, we propose the weighted 2-stage Booth algorithm. The synthesis results show that the multiplier using the proposed algorithm achieves better power-delay products than those achieved by conventional Booth multipliers. We believe that the proposed Booth algorithm can be broadly utilized in general processors as well as digital signal processors, mobile application processors, and various arithmetic units that use Booth encoding.

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A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

Cited by 47 publications

References 8 publications

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

A multi-format floating-point multiplier for power-efficient operations

Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

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