A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

Cha, Hyouk-Kyu; Yun, Ilhyun; Kim, Jin Bong; So, Byeong-Cheol; Chun, Kanghyup; Nam, In-Hyun; Lee, Kwyro

doi:10.1109/jssc.2006.880603

Cited by 58 publications

(22 citation statements)

References 17 publications

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“…(1) The set of the voltage value The intrinsic gate oxide breakdown voltage is 5.8V [4] in 180nm standard CMOS technology. Considering the voltage drop in the test chip and the deviation, we choose 6V 6.5V 7V 7.5V 8V for study.…”

Section: Experiments Schemementioning

confidence: 99%

A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features

2016

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Abstract. The program consistency of high density gate-oxide anti-fuse PROM (programmable read only memory) memory cell is considered in this paper. To solve this problem, we do research on the mechanism and models of gateoxide break down. A test chip based on 2T memory cell is also designed for the experiment. During the test, we have found that the program consistency of 2T cell is really pessimistic. What's more, the program voltage has effect on the consistency. Through research and test, we have got the optimal program voltage-6.5V for 2T memory cell in 180nm technology. To further improve the consistency, we modify the 2T memory cell and propose a 3T memory cell. It consumes 18% more area, but the standard deviation of equivalent resistance decreases 15.3% in the worst situation. The deviation can decrease 80.3% at most. The program consistency is greatly improved.

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Section: Experiments Schemementioning

confidence: 99%

A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features

2016

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“…It is usually used for the redundancy memory of dynamic random access memory (DRAM) or static RAM (SRAM) [1][2][3][4]. This antifuse cell is costeffective because its fabrication process is compatible with CMOS baseline process.…”

Section: Introductionmentioning

confidence: 99%

On-State Resistance Instability of Programmed Antifuse Cells during Read Operation

Han¹,

Lee²,

Kim³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…NVM (Non-volatile memory) for power management IC (PMIC) is generally eFuse (Electrical fuse) type or antifuse type OTP (One-time programmable) memory which is small-area and does not require optional processes instead of EEPROM or flash memory [1,2]. The OTP memory of antifuse type is programmed by electrically shorting with a breakdown mechanism when a high voltage is applied to thin gate oxides [3].…”

Section: Introductionmentioning

confidence: 99%

Design of 1-Kb eFuse OTP Memory IP with Reliability Considered

Kim¹,

Kim²,

Jin³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 µA to 61 µA when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 kΩ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

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A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

Cited by 58 publications

References 17 publications

A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features

A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features

On-State Resistance Instability of Programmed Antifuse Cells during Read Operation

Design of 1-Kb eFuse OTP Memory IP with Reliability Considered

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