Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability.
This paper presents an improved tool called FITVS( Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and FPGA emulation, and the speed of injection can reach the order of 1us/fault.
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