FITVS: A FPGA-Based Emulation Tool For High-Efficiency Hardness Evaluation

Zheng, H.; Lu, Fan; Yue, Suge

doi:10.1109/ispa.2008.46

Cited by 7 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Approaches like FITVS [19] and NETFI [20] that modify the FPGA primitives library are problematic because this modification has to be done for each FPGA family and vendor to be supported. Moreover, no separation between FI logic and the DUT's logic is possible as the output is only one fault-injected netlist.…”

Section: Discussionmentioning

confidence: 99%

“…Zheng, Fan, and Yue (FITVS) [19] as well as Mansour and Velazco (NETFI) [20], and Pellegrini et al (Crash-Test) [21] implement FI at the netlist level. All share the basic approach of synthesizing the DUT description first into Verilog or EDIF netlists before instrumenting these and/or the underlying technology-independent synthesis libraries with custom tools.…”

Section: Netlist-level Approachesmentioning

confidence: 99%

See 1 more Smart Citation

FIJI: Fault InJection Instrumenter

et al. 2019

View full text Add to dashboard Cite

FPGAs are increasingly used in safety-critical applications (e.g., in aerospace and automotive engineering). Safety standards stipulate that implemented countermeasures against run-time faults such as detection and isolation of affected components, automatic reconfiguration, and redundancy mechanisms must be adequately verified. To that end, fault injection tests by various means have been established as a suitable method. For such tests, faults can be provoked by radiation, simulation, or manipulating the design, for example, by inserting additional logic or manipulating the synthesis flow. This work briefly summarizes the various fault injection approaches with a focus on methods that are capable of stressing critical nets of a design running on actual hardware without requiring to re-synthesize. While the state-of-the-art tools can work with complex designs, they often lack controllability of the exact timing of the injection events (which is important to track the system's response on faults in a logic simulation) and/or use a high amount of FPGA resources. To overcome these issues, we propose a resource-saving netlist-based fault injection framework Fault InJection Instrumenter (FIJI) that can target individual nets at test runtime. This paper presents FIJI's work flow, implementation details, and an evaluation in terms of FPGA resources, timing impact, and performance during instrumentation and test execution. The FIJI framework has been made publicly available by the authors under an open-source license.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Netlist-level Approachesmentioning

confidence: 99%

FIJI: Fault InJection Instrumenter

et al. 2019

View full text Add to dashboard Cite

show abstract

“…• FITVS [214] demonstrates the library-replace-modelling technique to insert saboteurs in the library modules for FI. Real time emulation is performed without FPGA reconfiguration.…”

Section: Emulated Fault Injectionmentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

View full text Add to dashboard Cite

This thesis is the result of my work as research assistant at the Institute for Communication Technologies and Embedded Systems (ICE) at the RWTH Aachen University. During this time I have been accompanied and supported by many people. It is my great pleasure to take this opportunity to thank them. My most sincere thanks go to my advisors, Prof. Anupam Chattopadhyay and Prof. Tobias Noll. Anupam has been extremely helpful and tremendously inspiring throughout my PhD study. Prof. Noll has been impressively knowledgeable while patient with my ideas and mistakes. Their thoughtful advices have greatly contributed to this work and influenced me for my future career. Special thanks go to my defense committee members, Prof. Andrei Vescan and Prof. Renato Negra for spending their time, offering oral exam, giving me feedback, and attending my defense session. Several colleagues in ICE and EECS have assisted and encouraged me during the past five years for my work and personal life. Among them I would like to show my deep appreciation to Ayesha Khalid, Zoltán Rákossy and Michael Meixner. Furthermore, I would like to thank my students

show abstract