Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits

Abstract

Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability.

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

“…Area-and Delay-optimized implementations are shown to have consistent reliability trends (Limbrick et al, 2011).…”

“…Identification of design characteristics that can be used by EDA tools to estimate reliability during the logic synthesis step. Logic depth, capacitance, and cell adjacency are presented as characteristics that relate to reliability (Limbrick et al, 2011;Limbrick and Robinson, 2012). …”

“…For the analysis in this chapter, P generation is assumed constant across all nodes in the circuit. P propagation is calculated probabilistically using a method introduced in (Asadi and Tahoori, 2005) and extended in (Limbrick et al, 2011 Figure 7.13: Pulse width vs. deposited charge for a two-input NAND cell with multiple drive strengths ("nand2x1", "nand2x2", "nand2x4") and three-and four-input NAND cells functioning as a two-input NAND cell ("nand3x1", "nand3x2", "nand4x1", "nand4x2").…”

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

“…However, strategies that modify or evaluate the actual synthesis behavior [11] are less frequently seen. There are approximate logic synthesis techniques available [12][13] [14],…”

Constraint propagation in physical design of circuits

“…Ly and Girczyc [34] implemented three types of applications for constraint propagation and demonstrated the propagation power in an IC design environment. Limbrick , et al [35] investigated the impact of synthesis constraints on error propagation probability of circuits, and analysed the relationship between delay, area, and mapping effort and error propagation probability, separately. Later, they further analysed the power and reliability of the circuit under performance constraints [36].…”