A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Jacquet, D.; Hasbani, Frédéric; Flatresse, Philippe; Wilson, Robin; Arnaud, F.; Cesana, Giorgio; Gilio, Thierry Di; Lecocq, Christophe; Roy, Tanmoy; Chhabra, Amit; Grover, Chiranjeev; Minez, Olivier; Uginet, J.; Durieu, Guy; Adobati, Cyril; Casalotto, Davide; Nyer, F.; Menut, Patrick; Cathelin, Andreia; Vongsavady, Indavong; Magarshack, Philippe

doi:10.1109/jssc.2013.2295977

Cited by 120 publications

(55 citation statements)

References 19 publications

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“…In addition, body biasing can give an extra edge. In FD-SOI back-bias voltage can be varied from -3V Reverse Body Biasing (RBB) using conventionalwell transistors up to +3V Forward Body Biasing (FBB) using flip-well transistors [5]. Applying such a strong bias has a significant impact on the leakage performance trade-off as the threshold voltage of transistors varies by 85mV when the bias voltage value is changed by 1V.…”

Section: A Process Technologymentioning

confidence: 99%

“…With respect to voltage scaling, forward body biasing allows to speed-up transitions between the normal and boost modes. For example, the back-bias voltage of a 5mm 2 Cortex A9 processor can switch between 0V and 1.3V in less than 1µs [5]. 3) Achieve state-retentive leakage management.…”

Section: A Process Technologymentioning

confidence: 99%

“…3) Achieve state-retentive leakage management. With RBB, we can temporarily enter low-leakage sleep mode, reducing leakage power by up to an order of magnitude [5]. With respect to traditional power gating techniques, body biasing allows faster transitions between the two modes, and is intrinsically state-retentive.…”

Section: A Process Technologymentioning

confidence: 99%

“…Power models 1) Cores: To evaluate the performance and energyefficiency of the presented server platform, we extract a performance and power model from state-of-the-art manufactured ARM-v8 devices and 28nm FD-SOI STM test chips [5]. We combine the 28nm FD-SOI power and performance model of a recent Cortex A9 implementation of STM in 28nm bulk and FD-SOI, considering the differences in pipeline length ratio and critical path between Cortex A57 and Cortex A9.…”

Section: B Server Architecturementioning

confidence: 99%

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Towards Near-Threshold Server Processors

Pahlevan¹,

Picorel²,

Pourhabibi³

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-The popularity of cloud computing has led to a dramatic increase in the number of data centers in the world. The ever-increasing computational demands along with the slowdown in technology scaling has ushered an era of power-limited servers. Techniques such as near-threshold computing (NTC) can be used to improve energy efficiency in the post-Dennard scaling era. This paper describes an architecture based on the FD-SOI process technology for near-threshold operation in servers. Our work explores the trade-offs in energy and performance when running a wide range of applications found in private and public clouds, ranging from traditional scale-out applications, such as web search or media streaming, to virtualized banking applications. Our study demonstrates the benefits of near-threshold operation and proposes several directions to synergistically increase the energy proportionality of a near-threshold server.

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Section: A Process Technologymentioning

confidence: 99%

Section: A Process Technologymentioning

confidence: 99%

Section: A Process Technologymentioning

confidence: 99%

Section: B Server Architecturementioning

confidence: 99%

See 2 more Smart Citations

Towards Near-Threshold Server Processors

Pahlevan¹,

Picorel²,

Pourhabibi³

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…5.5.1 [4]. The buried oxide (BOX) underneath the active devices isolates the drains and sources from the bulk, allowing the transistor body to be used as a back-gate, hence enabling significant threshold voltage (Vt) shifts.…”

mentioning

confidence: 99%

5.5 A forward-body-bias tuned 450MHz Gm-C 3^rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply

Lechevallier

Struiksma

Sherry

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible with opamp-RC techniques. The inverter's class-AB behavior, together with the high transconductance per quiescent current, results in a high dynamic range per power when optimally biased [3]. The major disadvantage of traditional inverter-based Gm-C filters is that they are tuned with the supply voltage (VDD), hence requiring a finely controllable supply. Voltage regulators used to accomplish this imply a voltage headroom (including margin for tuning) and degrade total power efficiency by tens of percent. In this paper, we show that by exploiting body biasing in an Ultra-Thin BOX and Body, Fully-Depleted SOI (UTBB FD-SOI) CMOS technology, we overcome the requirement for a tunable VDD in inverter-based Gm-C filters, while achieving a high linearity over a wide supply voltage range. Without body biasing, Gm changes and linearity is degraded. For high VDD, the inverter behavior is compressive (mobility reduction), while for low VDD it is expansive (exponential region). Only one VDD results in a flat Gm-curve, which means that it produces little 3rd order distortion. Body biasing can be applied to tune Gm back to its nominal value over different VDD, without linearity degradation, as illustrated in the bottom right plot of Fig. 5.5.1. We apply this technique to a low-pass (LP) Gm-C filter to keep the cut-off frequency (Fc) constant and to guarantee high linearity over a 300mV supply voltage range. Local supply decoupling is still required, but the separate voltage regulator can be omitted. Without this technique, the same supply variation would have shifted the cut-off frequency between 110 and 650MHz and degraded IIP3 by more than 10dB.The LP filter topology shown in Fig. 5.5.2 is derived from a 3rd order, doubly terminated Butterworth LC ladder prototype using gyrator synthesis [1]. The transconductors and MOM capacitors are sized for a nominal Fc of 450MHz. The use of 110nm gate

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The Plural Many‐core Architecture – High Performance at Low Power

Ginosar

2021

Multi‐Processor System‐on‐Chip 1

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A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Cited by 120 publications

References 19 publications

Towards Near-Threshold Server Processors

Towards Near-Threshold Server Processors

5.5 A forward-body-bias tuned 450MHz Gm-C 3^rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply

The Plural Many‐core Architecture – High Performance at Low Power

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A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Cited by 120 publications

References 19 publications

Towards Near-Threshold Server Processors

Towards Near-Threshold Server Processors

5.5 A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply

The Plural Many‐core Architecture – High Performance at Low Power

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Product

Resources

About

5.5 A forward-body-bias tuned 450MHz Gm-C 3^rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply