5.5 A forward-body-bias tuned 450MHz Gm-C 3^rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply

Abstract

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible with opamp-RC techniques. The inverter's class-AB behavior, together with the high transconductance per quiescent current, results in a high dynamic range per power when optimally biased [3]. The major disadvantage of traditional inverter-based Gm-C filters is that they are tuned with the supply voltage (VDD), hence requiring a finely controllable supply. Voltage regulators used to accomplish this imply a voltage headroom (including margin for tuning) and degrade total power efficiency by tens of percent. In this paper, we show that by exploiting body biasing in an Ultra-Thin BOX and Body, Fully-Depleted SOI (UTBB FD-SOI) CMOS technology, we overcome the requirement for a tunable VDD in inverter-based Gm-C filters, while achieving a high linearity over a wide supply voltage range. Without body biasing, Gm changes and linearity is degraded. For high VDD, the inverter behavior is compressive (mobility reduction), while for low VDD it is expansive (exponential region). Only one VDD results in a flat Gm-curve, which means that it produces little 3rd order distortion. Body biasing can be applied to tune Gm back to its nominal value over different VDD, without linearity degradation, as illustrated in the bottom right plot of Fig. 5.5.1. We apply this technique to a low-pass (LP) Gm-C filter to keep the cut-off frequency (Fc) constant and to guarantee high linearity over a 300mV supply voltage range. Local supply decoupling is still required, but the separate voltage regulator can be omitted. Without this technique, the same supply variation would have shifted the cut-off frequency between 110 and 650MHz and degraded IIP3 by more than 10dB.The LP filter topology shown in Fig. 5.5.2 is derived from a 3rd order, doubly terminated Butterworth LC ladder prototype using gyrator synthesis [1]. The transconductors and MOM capacitors are sized for a nominal Fc of 450MHz. The use of 110nm gate

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“…As previously demonstrated in [10][11][12][13], body-biasing techniques have been profitably used for compensating process, voltage, and temperature (PVT) variations, and for tuning circuit performance. Two gate oxide options are available for both RVT and LVT configuration.…”

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“…Unlike in bulk CMOS technologies, the range of forward body bias (FBB) voltages is not restricted since the BOX eliminates the parasitic diodes between the bulk and the source/drain terminals. The low-V T H (LVT) transistors in the 28 nm UTBB FDSOI CMOS process are fabricated as 'flip-well' devices where the NMOS and PMOS devices are placed in the N-well and P-well respectively [51]. …”