A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Hodjat, A.; Hwang, D.; Lai, Bo-Cheng; Tiri, Kris; Verbauwhede, Ingrid

doi:10.1145/1057661.1057677

Cited by 53 publications

(28 citation statements)

References 11 publications

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“…Though AES and SOSEMANUK are structurally different, it is interesting to note that the highest throughput obtained in our SOSEMANUK implementation outperforms stateof-the-art AES (both software and hardware) implementations [28,41,24,12,27].…”

Section: Benchmarking With Other Implementationsmentioning

confidence: 87%

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes

Paul

Chattopadhyay

2016

IEEE Trans. Comput.

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With increasing usage of hardware accelerators in modern heterogeneous Systemon-Chips (SoCs), the distinction between hardware and software is no longer rigid. The domain of cryptography is no exception and efficient hardware design of so-called software ciphers are becoming increasingly popular. In this paper, for the first time we propose an efficient hardware accelerator design for SOSEMANUK, one of the finalists of the eSTREAM stream cipher competition in the software category. Since SOSEMANUK combines the design principles of the block cipher Serpent and the stream cipher SNOW 2.0, we make our design flexible to accommodate the option for independent execution of Serpent and SNOW 2.0. In the process, we identify interesting design points and explore different levels of optimizations. We perform a detailed experimental evaluation for the performance figures of each design point. The best throughput achieved by the combined design is 67.84 Gbps for SOSEMANUK, 33.92 Gbps for SNOW 2.0 and 2.12 Gbps for Serpent. Our design outperforms all existing hardware (as well as software) designs of Serpent, SNOW 2.0 and SOSEMANUK, along with those of all other eSTREAM candidates.

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Section: Benchmarking With Other Implementationsmentioning

confidence: 87%

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes

Paul

Chattopadhyay

2016

IEEE Trans. Comput.

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“…For example, the SHA-256 hashing on a dedicated crypto-engine clocked at 170MHz requires 0.125 cycles/byte according to [32], which is about 10x faster than the software implementation reported in Table V. As another example, AES encryption performed on a separate engine clocked at 340MHz requires 0.69 cycles/byte [19], which is about 1.6x faster than encryption that uses Intel's AES-NI instructions. Note that with a crypto-engine, the encryption can be done in the background, freeing up the CPU core to continue execution.…”

Section: B Overhead Of Compartment Operationsmentioning

confidence: 99%

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

Evtyushkin

Elwell

Özsoy

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-We consider the problem of how to provide an execution environment where the application's secrets are safe even in the presence of malicious system software layers. We propose Iso-X -a flexible, fine-grained hardware-supported framework that provides isolation for security-critical pieces of an application such that they can execute securely even in the presence of untrusted system software. Isolation in Iso-X is achieved by creating and dynamically managing compartments to host critical fragments of code and associated data. Iso-X provides fine-grained isolation at the memory-page level, flexible allocation of memory, and a low-complexity, hardwareonly trusted computing base. Iso-X requires minimal additional hardware, a small number of new ISA instructions to manage compartments, and minimal changes to the operating system which need not be in the trusted computing base. The run-time performance overhead of Iso-X is negligible and even the overhead of creating and destroying compartments is modest. Iso-X offers higher memory flexibility than the recently proposed SGX design from Intel, allowing both fluid partitioning of the available memory space and dynamic growth of compartments. An FPGA implementation of Iso-X runtime mechanisms shows a negligible impact on the processor cycle time.

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“…A full encryption of 128-bit data using a 128-bit key takes precisely eleven cycles. For a detailed discussion on the architecture, the reader is referred to [4]. …”

Section: Aes-based Cryptographic Enginementioning

confidence: 99%

Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

Tiri

Hwang

Hodjat

et al. 2005

Cryptographic Hardware and Embedded Systems – CHES 2005

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114

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Abstract. Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18µm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

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A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Cited by 53 publications

References 11 publications

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

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