Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes

Abstract

With increasing usage of hardware accelerators in modern heterogeneous Systemon-Chips (SoCs), the distinction between hardware and software is no longer rigid. The domain of cryptography is no exception and efficient hardware design of so-called software ciphers are becoming increasingly popular. In this paper, for the first time we propose an efficient hardware accelerator design for SOSEMANUK, one of the finalists of the eSTREAM stream cipher competition in the software category. Since SOSEMANUK combines the design principles of the block cipher Serpent and the stream cipher SNOW 2.0, we make our design flexible to accommodate the option for independent execution of Serpent and SNOW 2.0. In the process, we identify interesting design points and explore different levels of optimizations. We perform a detailed experimental evaluation for the performance figures of each design point. The best throughput achieved by the combined design is 67.84 Gbps for SOSEMANUK, 33.92 Gbps for SNOW 2.0 and 2.12 Gbps for Serpent. Our design outperforms all existing hardware (as well as software) designs of Serpent, SNOW 2.0 and SOSEMANUK, along with those of all other eSTREAM candidates.

Compact Reconfigurable Architecture for Sosemanuk Stream Cipher

“…This work uses 992 bytes of memory for S-box implementations without affecting performance of Serpent24 block cipher. Sosemanuk achieved throughput of 4.281 Gbps at a clock frequency of 133.788 MHz, where as other architectures [3] and [9] achieved throughput better than proposed architecture. Proposed architecture uses less hardware and consumes less energy as compared to other [3] and [9] architectures.…”

“…These trends are increasing demand for hardware implementation of software based stream ciphers. Considering SOC design aspects proposed work considers hardware implementation of software based stream cipher Sosemanuk [3].…”

Optimized architecture for SNOW 3G

“…Hardware implementation of the cryptographic algorithm on FPGA devices is attractive solutions because FPGAs are reconfigurable [2][3][4][5][6][7][8]. This property provides flexibility for dynamic system development and capable of implementing a wide range of functions/architectures/algorithms.…”