Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

Tiri, Kris; Hwang, D.; Hodjat, A.; Lai, Bo-Cheng; Yang, Shenglin; Schaumont, Patrick; Verbauwhede, Ingrid

doi:10.1007/11545262_26

Cited by 118 publications

(56 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2-1 [10]. Possible candidates of physical roots of trust are: true random number generators or TRNGs [21]- [22] harvest random numbers from truly physical sources of randomness and can therefore be trusted to produce highly random keys for cryptographic purposes; design styles for digital silicon circuits have been developed which minimize and ideally eliminate certain physical side channels [23]; physically unclonable functions produce unpredictable and instance-specific values and can be used to provide physically secure key generation and storage. …”

Section: Information Securitymentioning

confidence: 99%

X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices

Wang

Zhang

Liao

et al. 2018

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Section: Information Securitymentioning

confidence: 99%

X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices

Wang

Zhang

Liao

et al. 2018

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

“…less balanced) but easier to implement solutions based on standard static non-balanced gate libraries (see e.g. motivation to use WDDL from [6]). …”

Section: Dynamic Logic and Securitymentioning

confidence: 99%

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Kulikowski

Smirnov

Taubin

2006

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite their benefits for security applications they have not been adapted to current mainstream designs due to the lack of electronic design automation support and their nonstandard or proprietary design methodologies. We present a novel asynchronous fine-grain pipeline synthesis methodology that addresses these limitations. It allows synthesis of asynchronous quasi delay insensitive circuits from standard high-level hardware description language (HDL) specifications. We briefly present a proof of concept differential dynamic power balanced micropipeline library cells that are approximately 6 times more balanced than the best (differential dynamic) cells designed using previous balancing methods. An implementation of the Advanced Encryption Standard based on these balanced cells and synthesized using our tool flow shows a 6.6 times throughput improvement over the synchronous automatically pipelined implementation using the same TSMC 0.18μm technology synthesized from the same HDL specification.

show abstract

“…However, for some metrics it is necessary to take certain design choices into account. We have chosen to use WDDL [16,17] as an example of a secure logic style. All figures for silicon area, critical path, and power consumption are given for an implementation based on a 0.13 μm standard-cell library.…”

Section: Security and Performance Analysismentioning

confidence: 99%

“…For the solutions employing a secure logic style (options 1 and 3), this factor solely depends on the security of the chosen logic style. For a careful implementation of WDDL in an ASIC, an empirical evaluation has shown this factor to be over 750 [16].…”

Section: Securitymentioning

confidence: 99%

Power Analysis Resistant AES Implementation with Instruction Set Extensions

Tillich

Großschädl

Cryptographic Hardware and Embedded Systems - CHES 2007

View full text Add to dashboard Cite

Abstract. In recent years, different instruction set extensions for cryptography have been proposed for integration into general-purpose RISC processors. Both public-key and secret-key algorithms can profit tremendously from a small set of custom instructions specifically designed to accelerate performance-critical code sections. While the impact of instruction set extensions on performance and silicon area has been widely investigated in the recent past, the resulting security aspects (i.e. resistivity to side-channel attacks) of this particular design approach remain an open research topic. In this paper we discuss and analyze different techniques for increasing the side-channel resistance of AES software implementations using instruction set extensions. Furthermore, we propose a combination of hardware and software-related countermeasures and investigate the resulting effects on performance, cost, and security. Our experimental results show that a moderate degree of protection can be achieved with a simple software countermeasure. Hardware countermeasures, such as the implementation of security-critical functional units using a DPA-resistant logic style, lead to much higher resistance against side-channel attacks at the cost of a moderate increase in silicon area and power consumption.

show abstract

Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

Cited by 118 publications

References 12 publications

X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices

X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Power Analysis Resistant AES Implementation with Instruction Set Extensions

Contact Info

Product

Resources

About