A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V

Sinangil, Mahmut E.; Mair, Hugh; Chandrakasan, Anantha P.

doi:10.1109/isscc.2011.5746310

Cited by 56 publications

(28 citation statements)

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“…Conventional SRAMs cannot work at low-voltage levels due to stability problems. Thus, recent work has focused on implementing different bit-cell topologies [7,6] and peripheral assist circuits [21,33] to enable operation down to sub-VT levels.…”

Section: Intra-core Adaptationmentioning

confidence: 99%

Self-aware computing in the Angstrom processor

Hoffmann¹,

Holt²,

Kurian³

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Addressing the challenges of extreme scale computing requires holistic design of new programming models and systems that support those models. This paper discusses the Angstrom processor, which is designed to support a new Self-aware Computing (SEEC) model. In SEEC, applications explicitly state goals, while other systems components provide actions that the SEEC runtime system can use to meet those goals. Angstrom supports this model by exposing sensors and adaptations that traditionally would be managed independently by hardware. This exposure allows SEEC to coordinate hardware actions with actions specified by other parts of the system, and allows the SEEC runtime system to meet application goals while reducing costs (e.g., power consumption).

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Section: Intra-core Adaptationmentioning

confidence: 99%

Self-aware computing in the Angstrom processor

Hoffmann¹,

Holt²,

Kurian³

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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show abstract

“…9. To avoid the half-select issue, Sinangil et al [11] delays the boost until partway through the wordline pulse, so that half-selected cells have already started reading and the bitline voltage matches the internal voltage more closely. Fig.…”

Section: ) Effect Of Negative Cell Gnd As a Readability Assistmentioning

confidence: 99%

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer

Toh

et al. 2012

IEEE Trans. Circuits Syst. II

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“…In [11], the capacitively boosted word-line above power supply voltage (V DD ) would make the pass-gate device stronger, resulting in improved write-margin. The coupling happens once the word-line voltage reaches full V DD and is floated.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

“…As with using the word-line boosting technique for improving the write-margin [11], this technique should consider the timing delay issue for boost as well as the pass-gate device's leakage in unselected rows. Lastly but not least, in [11][12][13], the cell supply voltage (V DD ) was dynamically collapsed in the write-operation. This was implemented with a supply switch to the 2nd supply or floating voltage.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

“…However, the key technical issue depends on the data-retention voltage (DRV) of unselected bit-cells in the same column. If the collapsed V DD is higher than the DRV [11,12], the data stored would not be lost but would require a certain amount of restoring time. If the collapsed V DD is lower than the DRV to achieve the maximum benefit from using the write-assist technique [13], the bit-cell is essentially shut off.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

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Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability (V WL,OPT = 1.055 V) as well as to lower the minimum operating voltage for the read and write operations simultaneously (V MIN,READ = 0.58 V, V MIN,WRITE = 0.82 V for supply voltage (V DD ) = 1.1 V).

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A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V

Cited by 56 publications

References 1 publication

Self-aware computing in the Angstrom processor

Self-aware computing in the Angstrom processor

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

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