A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

Hayashi, Isamu; Amano, Tsuyoshi; Watanabe, Naoya; Yano, Yuji; Kuroda, Yasushi; Shirata, Masaya; Dosaka, K.; Nii, Koji; Noda, Haruhiko; Kawai, H.

doi:10.1109/jssc.2013.2274888

Cited by 65 publications

(27 citation statements)

References 14 publications

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“…However, its sensing speed and robustness are compromised due to the use of a level shifter. [7] utilizes a cross-coupled comparator with isolated input nodes to speed up the sensing delay while ML voltage swing is controlled by an on-chip down converter and a reference generator. It requires a ML swing of only 300 mV with a sensing time of about 2ns.…”

Section: B Low-swingml Schemementioning

confidence: 99%

State of the art ML sensing schemes for low-power CAM in nano-scale CMOS technologies

Yeo

2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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Content Addressable Memories (CAM) are used extensively in network routers for extremely fast search operation. In the latest Internet Protocol revision (IPv6), each entry has 128 bits (4x longer than 32-bit of IPv4) to provide enough address space for future usage. However, the wider word length of IPv6 standard leads to a substantial increase in sensing delay and power consumption of CAM. This short paper reviews recently published ML sensing schemes, focusing on low-power, high-speed designs implemented in nano-scale CMOS technology.

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Section: B Low-swingml Schemementioning

confidence: 99%

State of the art ML sensing schemes for low-power CAM in nano-scale CMOS technologies

Yeo

2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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“…In order to comply with the Classless Interdomain Routing (CIDR) [13], CAMs have also been equipped with ternary features, to support wildcard bits of network subnets, that mask the stored RIB-prefixes at arbitrary bit-positions with a "logical X" value [10]. Early fast demonstrations of such Ternary CAM (T-CAM) devices built on 250 nm Complementary Metal-Oxide-Semiconductor (CMOS) nodes supported content comparisons at 260 MHz [14], while similar T-CAMs at 180 nm [15], 130 nm [16], or 62 nm [17] CMOS nodes achieved maximum frequencies of 210 MHz, 200 MHz, and 400 MHz, respectively. Despite the rich variety of optimization techniques of mature electronic technology, state of the art electronic CAMs are scaling at a slow growth rate [18,19], and even by shifting to advanced 28 nm CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) [20], only footprint and power reductions have been achieved, with frequencies still lying around 370 MHz.…”

Section: Introductionmentioning

confidence: 99%

“…These results imply that electronic T-CAMs are hard-limited by the underlying interconnect network and can rarely reach the barrier of 1 Gb/s. This barrier was only recently broken using alternative non-optimal techniques that may use early predict/late-correct schemes [21], which are yet known to be heavily dependent on data patterns [17]. A second speed enhancement technique suggests inserting four T-CAM arrays performing in parallel at a slower rate of 4 × 400 MHz [6], necessitating even more complex Application Specific Integrated Circuit (ASIC) for deserialization and further exacerbating the energy requirements of routers, which reached their rack-power density limits in 2005 [4,22,23].…”

Section: Introductionmentioning

confidence: 99%

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

et al. 2017

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Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the "logical X" value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.

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“…The higher the offset, the higher is the power consumption and the sense delay. Many small memories (Non Volatile Memories and lowvoltage SRAMs) employ voltage-mode sense amplifier (VSA), [21][22][23] with a long BL developing time to provide tolerance for BL and SA offset; however, this is accomplished at the cost of reduced read speed. Cascodecurrent-load CSAs (CCL-CSAs), [24][25], require long BL settling times and have a small 1st-stage voltage difference when reading a small cell current (I CELL ).…”

Section: Introductionmentioning

confidence: 99%

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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The importance of embedded memory in contemporary multi-core processors and system-on-chip (SoC) for wearable electronics and IoT applications is growing. Intensive data processing in such processors and SoCs necessitates larger on-chip, energy-efficient static random access memory (SRAM). However, there are several challenges associated with low-voltage SRAMs. In this paper we have discussed the major hurdles at technology front for low power and robust SRAM design. We have discussed the different circuit techniques to mitigate these severe reliability concerns for embedded SRAM. Furthermore, this paper presented the recent development in embedded memory technology targeted to efficient computation. We have analyzed the effect of various device sizing on memory stability. The novel current mode circuit is also presented for high speed, offset tolerant SRAM sense amplifier. The FinFET memory design is explored to reduce the external manifestation of device mismatch on SRAM stability and memory yield.Keywords-Current Latch Sense Amplifier, Offset, SRAM, inter die variations, intra die variations.

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A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

Cited by 65 publications

References 14 publications

State of the art ML sensing schemes for low-power CAM in nano-scale CMOS technologies

State of the art ML sensing schemes for low-power CAM in nano-scale CMOS technologies

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

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