A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and &gt;30 dB SNDR at Nyquist in 14-nm CMOS FinFET

Kull, Lukas; Luu, Danny; Menolfi, Christian; Brändli, Matthias; Francese, Pier Andrea; Morf, Thomas; Kossel, Marcel; Cevrero, Alessandro; Özkaya, İlter; Toifl, Thomas

doi:10.1109/jssc.2018.2859757

Cited by 61 publications

(16 citation statements)

References 6 publications

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“…The ADC device occupies an area of 28 µm×30 µm. it is different from the research works of Liu et al [Liu, Chun, Kuo et al (2015); Polineni, Bhat and Rajan (2019); Kull, Luu, Menolfi et al (2018)] in achieving a higher sampling rate. The prototype high precision SAR ADC uses the supply voltage of from 0.6V to 0.9V.…”

Section: Measurement Resultsmentioning

confidence: 62%

High Precision SAR ADC Using CNTFET for Internet of Things

Gowrishankar¹,

Venkatachalam²

2019

Computers, Materials &Amp; Continua

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A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 µW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit. The proposed architecture has high scalability to CNTFET technology and also has higher energy efficiency. We compared the results of CNTFET based SAR ADC with other known architectures and confirm that this proposed SAR ADC can provide higher precision, power efficiency to the Internet of things node.

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Section: Measurement Resultsmentioning

confidence: 62%

High Precision SAR ADC Using CNTFET for Internet of Things

Gowrishankar¹,

Venkatachalam²

2019

Computers, Materials &Amp; Continua

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“…Therefore, referring to design strategy b), a significant amount of power can be saved. In fact, considering a frequency-divider-by-8 (with N=3 stages), the optimized strategy b) results in about 38% less power consumption with respect to the strategy a) 1 .However, it has to be noted that, since bias current of the source follower becomes negligible after the third or fourth DIV2 cell, this approach allows an effective power saving only in the first three or four stages.…”

Section: B Design With Optimized Div2mentioning

confidence: 99%

“…Most high speed integrated circuits such as time-interleaved analog to digital converters [1]- [2], clock and data recovery and building blocks for optical communication systems [3]- [4] and devices for clock and frequency synthesis in general [5]- [6], require high speed and low power frequency dividers.…”

Section: Introductionmentioning

confidence: 99%

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

Centurelli

Scotti

Trifiletti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110W thus confirming the advantages of the proposed approach.

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“…The interleaving factor is determined by: (i) the availability of low jitter clock generation and distribution at high frequencies; (ii) the time available for quantisation during the hold phase; (iii) the need to optimise power efficiency. A hierarchical approach has been adopted, where the first rank is 1‐to‐4, followed by two consecutive 1‐to‐4 ranks, resulting in 64

\times

time‐interleaving factor and allowing quantiser lanes optimised for power and area, such as the successive approximation register used in [1].…”

Section: Time‐interleaved Adc Front‐endmentioning

confidence: 99%

“…Introduction: Recent years have seen an increase in the number of published high-speed analogue-to-digital converters (ADCs) in the tens of GS/s speed and 6-8b resolution [1]. These developments are driven by a need for higher communication throughput in the wireless, wireline and optical domains, where digital processing promises more application flexibility and equalisation performance over their mixedsignal counterparts.…”

mentioning

confidence: 99%

80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold

Mattia

Murmann

2020

Electron. lett.

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An inverter-based track-and-hold circuit that merges the functions of buffering and sampling is proposed, simultaneously improving linearity, bandwidth and power efficiency when compared to stateof-the-art designs. The circuit operation and its governing equations are presented, and simulation results of an 80 GS/s, 5.5 ENOB timeinterleaved prototype consuming 25 mW from a 0.7 V supply demonstrate the advantages of the proposed topology using a predictive 7 nm FinFET CMOS technology.

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A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

Cited by 61 publications

References 6 publications

High Precision SAR ADC Using CNTFET for Internet of Things

High Precision SAR ADC Using CNTFET for Internet of Things

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold

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