A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Satpathy, Sudhir; Suresh, Vikram; Kumar, Raghavan; Gopal, Vinodh; Guilford, James; Yap, Kirk; Anders, Mark; Kaul, Himanshu; Agarwal, Amit; Hsu, Steven; Krishnamurthy, Ram; Mathew, Sanu

doi:10.1109/cicc.2019.8780272

Cited by 2 publications

(7 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, compared to Ref. [13], our work has a much lower power consumption. That is because the DSE Sbox is used as our Sbox, as opposed to the CFA Sbox in Ref.…”

Section: Comparisonmentioning

confidence: 87%

“…Refs. [10][11][12][13] proposed compact hardware implementations of SM4 by reducing the area cost of the Sbox. Refs.…”

Section: Dedicated Hardware Of Sm4mentioning

confidence: 99%

“…Refs. [14,15] merged multiple block ciphers into one hardware implementation, such as AES/SM4 [14] and Camellia/SM4/AES [15]. Refs.…”

Section: Dedicated Hardware Of Sm4mentioning

confidence: 99%

“…Ref. [13] implemented SM4 using 14 nm technology and two round functions to implement the encryption algorithm and the key expansion algorithm of SM4. Due to the advanced technology used, the throughput was much higher than ours.…”

Section: Comparisonmentioning

confidence: 99%

See 3 more Smart Citations

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

Chen

2022

Electronics

View full text Add to dashboard Cite

The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data should be protected against information leakage and data stealing. Deploying authenticated encryption with additional data (AEAD) algorithms on IoT devices ensures data confidentiality and integrity. However, AEAD algorithms are computationally intensive, while IoT devices are resource constrained or even battery powered. Therefore, a low-cost, low-power, and high-efficiency method of implementing an AEAD algorithm into resource-constrained IoT devices is required. The SM4-CCM algorithm, introduced in RFC 8998, is selected as the AEAD algorithm to address this problem. Algorithms similar to SM4-CCM (e.g., SM4 and AES-CCM) provide many architectural design references, but it is challenging to decide which architecture is the most suitable for SM4-CCM. In order to find the most efficient SM4-CCM hardware architecture, a design space exploration method is proposed. Firstly, the SM4-CCM algorithm is divided into five layers, and three candidate architectures are provided for each layer. Secondly, 63 design schemes for SM4-CCM are constructed by combining candidate architectures from each layer. Finally, a batch number of comparisons and analyses of experimental results are used to identify the most efficient one. Under TSMC 90 nm technology, the experimental results of the identified scheme show that the throughput, power consumption, and area achieve 199.99 Mbps, 1.625 mW, and 14.6 K gates, respectively. As a proof of concept, implementing this scheme on an FPGA board is also presented.

show abstract

“…However, compared to Ref. [13], our work has a much lower power consumption. That is because the DSE Sbox is used as our Sbox, as opposed to the CFA Sbox in Ref.…”

Section: Comparisonmentioning

confidence: 87%

“…Refs. [10][11][12][13] proposed compact hardware implementations of SM4 by reducing the area cost of the Sbox. Refs.…”

Section: Dedicated Hardware Of Sm4mentioning

confidence: 99%

“…Refs. [14,15] merged multiple block ciphers into one hardware implementation, such as AES/SM4 [14] and Camellia/SM4/AES [15]. Refs.…”

Section: Dedicated Hardware Of Sm4mentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%

See 2 more Smart Citations

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

Chen

2022

Electronics

View full text Add to dashboard Cite

show abstract

“…On the contrary, dynamic Huffman encoding constructs a Huffman tree according to the frequency of symbols [ 18 ]. By assigning a short-length code to the repeated symbols, dynamic Huffman encoding has an advantage of compression ratio [ 19 ]. As a result, static Huffman encoding shows a relatively low compression ratio compared with the dynamic Huffman encoding.…”

Section: Inflate Algorithmmentioning

confidence: 99%

Lossless Decompression Accelerator for Embedded Processor with GUI

Hwang

Cho

et al. 2021

Micromachines

View full text Add to dashboard Cite

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

show abstract

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Cited by 2 publications

References 6 publications

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

Lossless Decompression Accelerator for Embedded Processor with GUI

Contact Info

Product

Resources

About