2021
DOI: 10.3390/mi12020145
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Lossless Decompression Accelerator for Embedded Processor with GUI

Abstract: The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (S… Show more

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Cited by 6 publications
(4 citation statements)
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“…The essence of this method is its ability to identify sequential symbols, especially those with the longest match distances, and convert them into length and distance pairs. This allows the algorithm to efficiently compress files by pointing back to previous similar sequences instead of writing out each sequence afresh, leading to considerable data reduction [78,79].…”
Section: Deflate Image Compressionmentioning
confidence: 99%
“…The essence of this method is its ability to identify sequential symbols, especially those with the longest match distances, and convert them into length and distance pairs. This allows the algorithm to efficiently compress files by pointing back to previous similar sequences instead of writing out each sequence afresh, leading to considerable data reduction [78,79].…”
Section: Deflate Image Compressionmentioning
confidence: 99%
“…The intelligent monitoring device includes an edge AI module. We enabled low-power, high-efficiency computations by constructing systems with dedicated processors specifically designed for AI algorithm operations [ 21 , 22 , 23 , 24 , 25 ]. The accuracy of the vision-based monitoring system was analyzed to demonstrate the feasibility of the system.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, before designing a k-NN accelerator, it is necessary to review and optimize the structure of a k-NN accelerator suitable for a specific problem. It is similar to testing hardware logic in FPGA before application-specific integrated circuit (ASIC) [ 36 , 37 , 38 ]. Therefore, in order to overcome this problem, this study proposes an ASimOV framework that examines and optimizes various k-NN accelerators to generate HDL code that can be executed directly on the FPGA.…”
Section: Introductionmentioning
confidence: 99%