A 200 Mhz 0.8μm BiCMOS Modular Memory Family Of DRAM And Multiport SRAM

Silburt,; Phillips, Nicholas; Gibson, Peter G.; Bluschke,; Verma, Subhash; Diedrich, Christian; Kornachuk,; Fujimoto,; Nadeau-Dostie,

doi:10.1109/cicc.1992.591148

Proceedings of the IEEE Custom Integrated Circuits Conference

DOI: 10.1109/cicc.1992.591148

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A 200 Mhz 0.8μm BiCMOS Modular Memory Family Of DRAM And Multiport SRAM

Silburt Silburt¹,

Nicholas Phillips²,

Peter G. Gibson³

et al.

Abstract: A family of modular memories has been designed in a 0.8 pm BiCMOS process based on a synchronous self-timed architecture. Nominal access and cycle times are 5 ns for 64KBit blocks of 1, 2 and 4 port SRAM as well as a DRAM using a four transistor (4T) core cell.

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Cited by 2 publications

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Low-supply-noise Low-power Embedded Modular SRAM For Mixed Analog-digital ICs

Schultz¹,

Gibbins²,

Fujimoto³

et al.

Proceedings of the IEEE Custom Integrated Circuits Conference

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A low-power, low-noise embedded modular SRAM has been designed that dissipates 0.22 mWA4Hz and generates 25 mAlns dVdt for a 512 x 15 configuration at 3.3 V. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-power decoding techniques. 7.1.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-0246-x/32 $3.00 1992 IEEE

show abstract

Low-supply-noise Low-power Embedded Modular SRAM For Mixed Analog-digital ICs

Schultz¹,

Gibbins²,

Fujimoto³

et al.

Proceedings of the IEEE Custom Integrated Circuits Conference

View full text Add to dashboard Cite

show abstract

A logic-enhanced memory for digital data recovery circuits

Schultz¹,

Gulak²

1993 IEEE International Symposium on Circuits and Systems

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A 200 Mhz 0.8μm BiCMOS Modular Memory Family Of DRAM And Multiport SRAM

Abstract: A family of modular memories has been designed in a 0.8 pm BiCMOS process based on a synchronous self-timed architecture. Nominal access and cycle times are 5 ns for 64KBit blocks of 1, 2 and 4 port SRAM as well as a DRAM using a four transistor (4T) core cell.

Cited by 2 publications

References 8 publications

Low-supply-noise Low-power Embedded Modular SRAM For Mixed Analog-digital ICs

Low-supply-noise Low-power Embedded Modular SRAM For Mixed Analog-digital ICs

A logic-enhanced memory for digital data recovery circuits

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