A 200 MFlop CMOS Transformation Processor

Abstract

A 163 MFlop graphics processor is realized in a 0.7 micron 2-layer metal CMOS process for operating at 40MHz. The graphics processor provides 3.3 million transformed, perspective divided, clip tested 3-D vertices per second. The matrix multiplication is based on the Interleaved Multiplier Accumulator algorithm, which transposes the order of the arithmetic operations to accomplish the maximum throughput. The graphics processor is fully IEEE-754 singleprecision compliant. It occupies 100 square millimeters of silicon.6.1 .I IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCESimilarly, transformation matrix for y-axis rotation is R,(@ and I?,@) for z-axis rotation Any transformation involving translation, scaling or rotation can be done by cascading the transformation matrices into one equivalent transformation matrix and performed in the way illustrated in (EQ 1). 0-7803-0246-X/92 $3.00 1992 IEEE