A 20.5-dBm &lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$X$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt;-Band Power Amplifier With a 1.2-V Supply in 65-nm CMOS Technology

Trinh, Van‐Son; Nam, Hyohyun; Park, Jung‐Dong

doi:10.1109/lmwc.2018.2885305

Cited by 19 publications

(9 citation statements)

References 9 publications

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“…While operating at V DD = 1 V, the proposed PA has achieved a saturated output power of 20.7 dBm and 22.4% peak PAE at 10 GHz (23.5% peak PAE at 11 GHz). The PA also achieves an EC [20] of 117.5, which is among the best EC performances in recently reported X-band PAs in CMOS technology.…”

mentioning

confidence: 64%

“…Process Frequency (GHz) V DD (V) Publication Year [2] 180 nm CMOS 0-14 1.3 2004 [3] 180 nm CMOS 3.1-10.6 1.8 2005 [4] 180 nm CMOS 3-10 2 2006 [5] 180 nm CMOS 3.7-8.8 -2007 [6] 180 nm CMOS 6-10 1.5 2008 [7] 180 nm CMOS 8.5-10 3.3 2008 [8] 180 nm CMOS 4-17 3.6 2009 [9] 90 nm CMOS 5.2-13 2.8 2010 [10] 180 nm CMOS 7-12 3.6 2010 [11] 90 nm CMOS 5.2-13 -2010 [12] 180 nm CMOS 6.5-13 3.6 2011 [13] 180 nm CMOS 8.6-10.3 3 2011 [14] 45 nm CMOS SOI 4-50 1.1/6 2012 [15] 45 nm CMOS SOI 9-15 3.6/4.8 2013 [16] 45 nm CMOS SOI 10-32 0.75/1/2 2014 [17] 40 nm 3.5-9.5 1.2 2015 [18] 180 nm 7-10 3.3 2017 [19] 180 nm 3/9 3.6 2018 [20] 65 nm 8-11.4…”

Section: Referencementioning

confidence: 99%

“…A chip photograph of the fabricated PA is shown in Figure 14, and the chip size without pads is 0.90 mm × 0.37 mm (1.00 mm × 0.46 mm with pads). To assess the capability of the transistors in generating output power to the load with a variety of power supply, an EC defined in millisiemens (mS) [20] was used. To assess the capability of the transistors in generating output power to the load with a variety of power supply, an EC defined in millisiemens (mS) [20] was used.…”

Section: Fabrication and Measurementmentioning

confidence: 99%

“…Most of the reported X-band CMOS PA are implemented with 180 nm CMOS technology [2][3][4][5][6][7][8]10,12,13,18,19], while some others are with 90 [9,11] and 65 nm [20] CMOS technology. On the other hand, the authors of [14][15][16] showed the possibility of using shrinking 45 nm node to implement an X-band PA with reasonable performance.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, it can hardly supports modern modulation schemes, which require high linearity. Two other reported X-band PAs [7,20] achieve high output power utilizing two-stage cascode with TMN architecture. These two PAs achieve peak PAE of 24.5% and 19%, respectively.…”

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confidence: 99%

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A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

Yang

Lee

et al. 2020

Electronics

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For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

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mentioning

confidence: 64%