A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support

Golden, M.; Arekapudi, S.; Dabney, G.; Haertel, M.; Hale, S.; Herlinger, Lowell; Kim, Y.; McGrath, K.; Palisetti, Vasant; Singh, M.

doi:10.1109/isscc.2006.1696063

Cited by 13 publications

(6 citation statements)

References 3 publications

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“…For example, an AMD64 processor consumes 95 W at 2.6 GHz with dual cores in a 90-nm SOI process [11]. Assuming 2.0 MIPS/MHz/core of the Dhrystone 2.1 benchmark, the power-performance ratio is 109 MIPS/W as shown in Figure 15.…”

Section: Power Performance Ratio Comparisonmentioning

confidence: 99%

An Embedded Processor: Is It Ready for High-Performance Computing?

Arakawa

2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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High power-performance ratio is the most important factor in high-performance computing, whose performance is limited by its power budget. A SuperH TM (SH) embedded processor core, SH-X3, implemented in a 90-nm CMOS process running at 600 MHz achieved 1080 Dhrystone MIPS, 4.2 GFLOPS, and 55M polygons/s. Its power performance ratio reaches to as high as 3000 MIPS/W. It is, therefore, a candidate processor for high-performance computing. This paper focuses on the SH processors' low power features, floating-point architecture and performance, and applicability to the highperformance computing.

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Section: Power Performance Ratio Comparisonmentioning

confidence: 99%

An Embedded Processor: Is It Ready for High-Performance Computing?

Arakawa

2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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“…The existence of various arithmetic logic units (ALUs) in current superscalar processors [7,8] and different execution cores on the same chip [8][9][10] further worsen the problem, affecting circuit reliability and expanding cooling costs. At the same time, wide adders are also crucial for performance, and come into view inside the ALUs and floating point units (FPUs) of microprocessor datapaths.…”

Section: Introductionmentioning

confidence: 99%

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

Ibrahim

Gebali

2015

Microelectronics Journal

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“…To alleviate some clock woes, most high-speed chips now use grids [5,10,15,17,18,20]. These grids have the beneficial effect of averaging out the skew and jitter, but consume significant power.…”

Section: Introductionmentioning

confidence: 99%

Analysis of high-performance clock networks with RLC and transmission line effects

Condley

Guthaus

2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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Interconnect has come to be a dominant factor in on-chip signal propagation, skew and jitter. As frequencies increase, more accurate modeling of the wires is necessary in order to properly estimate clock propagation. However, most wire models for clock network synthesis are based on Elmore delay, a simple first-order RC model. In this work, we analyze the discrepancies between RC, RLC and transmission line models on both skew and jitter of clock trees and grids. From our experiments, the difference in skew can be as great as 45% of the clock period for transmission lines and 7.5% for the RLC model. We argue that a deeper investigation into accurately modeling long interconnect should become a higher priority in clock network synthesis.

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A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support

Cited by 13 publications

References 3 publications

An Embedded Processor: Is It Ready for High-Performance Computing?

An Embedded Processor: Is It Ready for High-Performance Computing?

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

Analysis of high-performance clock networks with RLC and transmission line effects

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