Abstract:Interconnect has come to be a dominant factor in on-chip signal propagation, skew and jitter. As frequencies increase, more accurate modeling of the wires is necessary in order to properly estimate clock propagation. However, most wire models for clock network synthesis are based on Elmore delay, a simple first-order RC model. In this work, we analyze the discrepancies between RC, RLC and transmission line models on both skew and jitter of clock trees and grids. From our experiments, the difference in skew can… Show more
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