Distributed LC Resonant Clock Grid Synthesis

Hu, Xuchu; Guthaus, Matthew R.

doi:10.1109/tcsi.2012.2190671

Cited by 23 publications

(22 citation statements)

References 34 publications

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“…The ISPD benchmarks are in a 45nm technology and use V dd of 1V and f 0 of 1GHz. The resonant benchmark designs are synthesized using the Resonant Clock Synthesis (ROCKS) methodology [6] and the C++ source code is modified for our new circuit techniques.…”

Section: Methodsmentioning

confidence: 99%

“…We then utilize C c insertion in parallel with L in a distributed resonant clock synthesis (ROCKS) [6] methodology. ROCKS starts similar to Meshworks [12] by creating an initial buffered grid.…”

Section: B Distributed Lc-tanksmentioning

confidence: 99%

“…Academic algorithms have further optimized these resonant clocks [5] and have shown to save up to 90% of the dynamic power at the expense of large inductor and decoupling capacitor on-chip area [6]. The inductor area is perhaps the most significant obstacle for significant power savings [5], [6].…”

Section: Introductionmentioning

confidence: 99%

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LC resonant clock resource minimization using compensation capacitance

Lin

Fahmy

Islam

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Distributed-LC resonant clock distribution is a viable technique to reduce clock distribution network (CDN) dynamic power. However, resonant clocks can require significant on-chip resources to form the inductors and decoupling capacitors which discourages adoption. This paper uses a compensation capacitor (Cc) to reduce the overhead of the on-chip inductor and capacitor resources without changing the performance of a distributed-LC resonant clock. Analysis on the ISPD clock benchmarks show nearly 12% reduction in passive device area compared to previous resonant clocks while still saving 49.9% power over traditional buffered clocks.

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Section: Methodsmentioning

confidence: 99%

Section: B Distributed Lc-tanksmentioning

confidence: 99%

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LC resonant clock resource minimization using compensation capacitance

Lin

Fahmy

Islam

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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“…Due to the capability of storing the energy in the inductors, the resonant clock networks provide the power saving effectively. Hu et al [6] proposed the first automated algorithm called resonant clock synthesis (ROCKS) including distributed LC tank placement and novel AC-based resonant grid buffer incremental placement optimization. Ahn et al [7] employed the power reduction techniques called Dynamic Voltage Frequency Scaling (DVFS) on the resonant network to maximize the synergy effect for the reduction in power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Step 1: Estimate average value of cluster matrix by using (6) Step 2: Estimate S.D. value of cluster matrix by using (7) Step 3: Estimate the window limit as, ( )…”

Section: Load Portioning Based Weight Updatementioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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Everything about the Clock

Xiu¹

2015

From Frequency to Time‐Average‐Frequency

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Distributed LC Resonant Clock Grid Synthesis

Cited by 23 publications

References 34 publications

LC resonant clock resource minimization using compensation capacitance

LC resonant clock resource minimization using compensation capacitance

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

Everything about the Clock

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