A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

Lee, Dong Uk; Lee, Hyun Woo; Kwean, Ki Chang; Choi, Young Kyoung; Moon, Hyong Uk; Kwack, Seung Wook; Kang, Shin Deok; Kim, Kwan Weon; Kim, Yong Ju; Choi, Young Jae; Moran, Patrick B.; Ahn, Joong Ho; Kih, Joong Sik

doi:10.1109/isscc.2006.1696091

Cited by 14 publications

(2 citation statements)

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“…DCC is divided into analog [6,7] and digital [1], [8][9][10][11][12] types according to the method of detecting the duty-cycle of the signal. Since analog DCC detects the duty-cycle by using capacitors, it takes a long time to settle and may cause duty fluctuations due to leakage current [11].…”

Section: Introductionmentioning

confidence: 99%

“…Thus, digital DCC is preferred in various applications, which is advantageous for maintaining duty-cycle corrected information, considering standby mode or power down mode [12]. In digital DCCs, there are methods using phase interpolation (PI) [8][9] and HCDL [1], [10][11][12]. The conventional PI method consists of tied two inverters with an output capacitor.…”

Section: Introductionmentioning

confidence: 99%

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A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

et al. 2023

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Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner-type DCC requires a large area and makes the DCC unsuitable for applications that operate at a wide-range frequency, such as memory or ADC interfaces. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line while maintaining the performance of the conventional DCC. The proposed DCC is divided into two operations. The training operation is performed for wide-range operation, followed by normal operation performed through the result of the training operation. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm 2 and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz. INDEX TERMSMemory interface, ADC interface, digital duty-cycle corrector (DCC), half-cycle delay line (HCDL), wide-range.FIGURE 1. Block diagram of the conventional DCC with HCDL.

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