A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

Wang, Yun; Lee, Hyun–Woo; Kim, Young‐Ju; Choi, Won-Jun; Shin, Sanghoon; Choi, Hyang-Hwa; Lee, Hyeng-Ouk; Kang, Shin-Deok; Moon, Hyong-Uk; Kwack, Seung-Wook; Lee, Dong Uk; Lee, Jungwoo; Choi, Young-Kyoung; Park, Nak-Kyu; Kwean, Ki-Chang; Kim, Kwan-Weon; Choi, Young-Jung; Ahn, Ji Hoon; Kih, Joongsik; Yang, Yeseok

doi:10.1109/asscc.2006.357916

Cited by 3 publications

(3 citation statements)

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“…1 [7], and the basic operation will be described below. There is a 180 degree phase difference between two delay loops, and each of them is locked-in to rising edge of buffered external clock (REFCLK) respectively.…”

Section: Proposed Dll Structurementioning

confidence: 99%

“…As the need for high performance applications extends, the need for high performance DRAM with low power consumption is increasing as well. Several DLLs have been presented for high performance [1][2][3][4][5][6][7]. However, as the operation frequency increases, power consumption and chip area increases due to additional circuit block for high frequency operation.…”

Section: Introductionmentioning

confidence: 99%

“…The focuses of this work are low power consumption and small area for low cost. In Section II, the architecture of the proposed DLL is described compared to previous DLL architecture [7]. This digital DLL has an open loop single replica block to achieve low power consumption and small area.…”

Section: Introductionmentioning

confidence: 99%

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A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM

Lee

Jin

Kim

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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this paper presents a low-power small-area open loop digital DLL. The DLL has open loop single replica block with duty cycle corrector (DCC), clock divider, pulse generator, 10-bit counter, and delay line. The DLL used for 2.2Gb/s/pin 2Gb DDR3 SDRAM is fabricated using 44nm DRAM Process. Experimental results show 1.1GHz operation frequency at 1.5V, and the measured total power and area savings in comparison with the conventional closed-loop operation is about 93.5% and 90.7% respectively.

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Section: Proposed Dll Structurementioning

confidence: 99%