2006 IEEE Asian Solid-State Circuits Conference 2006
DOI: 10.1109/asscc.2006.357916
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A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

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Cited by 3 publications
(3 citation statements)
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“…1 [7], and the basic operation will be described below. There is a 180 degree phase difference between two delay loops, and each of them is locked-in to rising edge of buffered external clock (REFCLK) respectively.…”
Section: Proposed Dll Structurementioning
confidence: 99%
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“…1 [7], and the basic operation will be described below. There is a 180 degree phase difference between two delay loops, and each of them is locked-in to rising edge of buffered external clock (REFCLK) respectively.…”
Section: Proposed Dll Structurementioning
confidence: 99%
“…As the need for high performance applications extends, the need for high performance DRAM with low power consumption is increasing as well. Several DLLs have been presented for high performance [1][2][3][4][5][6][7]. However, as the operation frequency increases, power consumption and chip area increases due to additional circuit block for high frequency operation.…”
Section: Introductionmentioning
confidence: 99%
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