A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM

Lee, Jong-Chern; Jin, Sin-Hyun; Kim, Dae-Suk; Ku, Young-Jun; Kim, Chul; Park, Byung-Kwon; Kim, Hong-Gyeom; Ahn, Sung Tae; Lee, Jaejin; Hong, Sung-Joo

doi:10.1109/asscc.2011.6123626

Cited by 4 publications

(2 citation statements)

References 6 publications

(7 reference statements)

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“…Moreover, the DLL also provides better jitter performance considering that there is no jitter accumulation in a voltage controlled delay line (VCDL) or digitally controlled delay line (DCDL). The application of DLL is not only limited to the clock synchronous but it is also useful for Double-Data-Rate Three (DDR3) SDRAM [1][2][3][4]. The advantages of an all-analog DLL are low jitter output and higher delay resolution.…”

Section: Introductionmentioning

confidence: 99%

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A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

Chen

Wang

et al. 2014

Sci. China Inf. Sci.

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A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667/800/1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG). To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps-1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm 2 . Keywords all-digital delay-locked loop, double-data-rate, digitally controlled delay line, shunt capacitor, thermometer code CitationChen H M, Ma S, Wang L, et al. A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller.

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Section: Introductionmentioning

confidence: 99%

“…An all-analog DLL is not suitable for the process portability and poor noise immunity. Therefore, digital DLL is developed to address these problems [3,4]. Digital DLL can get the extra advantages of less silicon area and deliver GDSII database quickly in around 3 weeks.…”

Section: Introductionmentioning

confidence: 99%