A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm

Han, Sangwoo; Kim, Jongsun

doi:10.1109/ipec.2012.6522683

Cited by 7 publications

(4 citation statements)

References 11 publications

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“…In order to achieve a memory bus data rate of over 400 Mbps/pin, DDR-x SDRAMs must incorporate an on-chip delay-locked loop (DLL) [1,2,3,4,5,6,7,8,9,10,11,12] that can eliminate skew problems and achieve higher timing margin at high frequencies. To design a DLL that can support both DDR3 and DDR4 specifications at the same time [13,14], the DLL should be locked within 512 clock cycles and operate over a frequency range from 300 MHz to 1.6 GHz using an internal supply voltage of less than 1.2 V. Also, the DLL must be capable of correcting the duty cycle of the distorted input clock so that the data-valid window (tDV) could be widened [2].…”

Section: Introductionmentioning

confidence: 99%

“…One of the reasons for using digital architectures is because DDR3/DDR4 SDRAMs require fast recovery times for various power mode transitions. To achieve a fast locking time, a successive approximation register (SAR)-based binary search algorithm was adopted in DLL designs [5,6,7,8,9]. However, this introduced harmonic lock problem [6,7,12].…”

Section: Introductionmentioning

confidence: 99%

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A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Yoon

Heo

Kim

2017

IEICE Electron. Express

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A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noisetolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02 mm 2 . The DLL operates over a frequency range of 0.3-2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48 mW from a 1.1 V supply at 1 GHz.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Yoon

Heo

Kim

2017

IEICE Electron. Express

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“…In addition, DLLs are often used in high-speed timeinterleaved and pipelined analog-to-digital converters (ADCs). In general, DLLs can be classified into three categories: analog [1,2], digital [3][4][5][6][7]12], and mixedmode type DLLs [8,9].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, a high-resolution dual-loop digital DLL is presented [12]. To resolve the low-resolution constraint in the conventional digital DLL, a new dual-loop (coarse + fine loop) architecture using a hybrid (binary + sequential) search algorithm is adopted.…”

Section: Introductionmentioning

confidence: 99%

A High-Resolution Dual-Loop Digital DLL

Kim¹,

Han²

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phaseinterpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-µm CMOS process, occupies an active area of 0.19 mm 2 and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pkpk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

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An anti-boundary switching fine-resolution digital delay-locked loop

Kim

2018

Analog Integr Circ Sig Process

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A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm

Cited by 7 publications

References 11 publications

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

A High-Resolution Dual-Loop Digital DLL

An anti-boundary switching fine-resolution digital delay-locked loop

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