2008 IEEE Asian Solid-State Circuits Conference 2008
DOI: 10.1109/asscc.2008.4708773
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A low power and high performance robust digital delay locked loop against noisy environments

Hyun–Woo Lee
1
,
Yun Wang
2
,
Jong-Jin Lee
3
et al.
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Cited by 3 publications
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A 2-locking-cycle skew-compensation circuit with the capability of tracking runtime-variations

Cheng
1
,
Wang
2
,
Chien
3
et al. 2010
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
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A 2-locking-cycle skew-compensation circuit with the capability of tracking runtime-variations

Cheng
1
,
Wang
2
,
Chien
3
et al. 2010
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
0
0
0
0
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A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Lee1,
Kim2,
Wang3
et al. 2010
Proceedings of 2010 IEEE International Symposium on Circuits and Systems
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Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces

Lee
1
,
Kim
2
2014
IEEE Trans. VLSI Syst.
12
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