A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

Nagamatsu, M.; Tanaka, S.; Mori, J.; Hirano, Koji; Noguchi, T.; Hatanaka, K.

doi:10.1109/4.52175

Cited by 70 publications

(24 citation statements)

References 5 publications

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“…Another multiplier implementation which uses the Wallace tree approach is the 54;54-bit regularly structured tree multiplier [19], proposed by Goto et al From the architectural point of view, this multiplier is very similar to those that have been described here [17,18]. Goto's multiplier uses Booth recoding and a Wallace tree of 4 : 2 compressors.…”

Section: Regularly Structured Tree Multipliermentioning

confidence: 99%

“…An important instance of this type of multiplier is the work by Nagamatsu et al [17,18]. The main characteristic of these implementations is that the complete Wallace tree of compressors is built and it is operated in a fully combinational fashion.…”

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

“…In this way, the latency of the multiplication operation is reduced to the minimum because a single step is required, and because there is no extra delay introduced by pipeline latches. Nagamatsu et al built a 32;32-bit multiplier [17] applying the modi"ed Booth algorithm to reduce the number of partial products by half, and using a Wallace tree of 4 : 2 compressors to sum the partial products as seen Fig. 7(a).…”

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

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Redundant arithmetic, algorithms and implementations

Gonzalez

Mazumder

2000

Integration

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Section: Regularly Structured Tree Multipliermentioning

confidence: 99%

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

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Redundant arithmetic, algorithms and implementations

Gonzalez

Mazumder

2000

Integration

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“…It can be implemented either by using two (3,2) counters or more efficiently directly from the truth table, achieving a 25 % reduction in propagation delay [16]. We have adopted a direct implementation as shown in figure 8 (padding elements for equalizing delays are included).…”

Section: (42) Countersmentioning

confidence: 99%

Fast multiplication in VLSI using wave pipelining techniques

Klass

Flynn

Goor

1994

Journal of VLSI Signal Processing

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Abstract. Wave pipelining is a design methodology that can increase the clock frequency of digital systems. Also known as maximum-rate pipelining, it has long been considered a technique for approaching the physical speed limit of a digital circuit. Unlike conventional pipelining, wave pipelining does not require internal clocked elements to increase throughput. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. In this article, we describe the design of a 16 x 16 wave-pipelined multiplier using a 1.0 ~m CMOS process. The multiplier is designed using a conventional static CMOS technology. Simulation results show a speedup of about 7x over a nonpipeline implementation.

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“…Modern multiplier designs use [4:2] adders [14] to reduce the PPR logic delay and regularize the layout. To improve regularity and compact layout, regularly structured tree (RST) with recurring blocks [6] and rectangular-styled tree by folding [8] were proposed, at the expense of more complicated interconnects.…”

Section: Introductionmentioning

confidence: 99%

High-performance left-to-right array multiplier design

Huang¹,

Ercegovac²

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n ≤ 32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split into upper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. The final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area and power than optimized tree multipliers while keeping the same delay for n ≤ 32.

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A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

Cited by 70 publications

References 5 publications

Redundant arithmetic, algorithms and implementations

Redundant arithmetic, algorithms and implementations

Fast multiplication in VLSI using wave pipelining techniques

High-performance left-to-right array multiplier design

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