Redundant arithmetic, algorithms and implementations

Gonzalez, A.F.; Mazumder, Pinaki

doi:10.1016/s0167-9260(00)00015-8

Cited by 32 publications

(5 citation statements)

References 44 publications

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“…there exist adders, that show only two discrete steps but require a much more complex logic what is caused by the fact that these adders are using operands to a base r ≥ 2. Details concerning this computer arithmetic stuff can be found in [4], [2].…”

Section: Ternary Addersmentioning

confidence: 99%

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Fey

2017

Preprint

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This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in O(1) and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset.

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Section: Ternary Addersmentioning

confidence: 99%

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Fey

2017

Preprint

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“…conventional 2's complement binary) additions are implemented using 6-input LUT devices. The redundant carry-save representation is also named as CS2 [5,20] representation in the literature, since each digit is represented by 2 bits. The redundant carry-save addition operation is represented in Figure 3.…”

Section: (63) Counters and Double Carry-save Arithmeticmentioning

confidence: 99%

An alternative carry-save arithmetic for new generation field programmable gate arrays

Cini¹,

Aktan²,

Morgul³

2016

Turk J Elec Eng & Comp Sci

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In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.

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“…For the multiplication operations, multiplier and multiplicand produces partial products which must be added up to have the multiplication result. The partial products can be added up using multioperand adders with parallel addition operands, or the products can be reduced using carry-free partial product reduction operators such as counter and compressor trees or signed-digit addition trees [3,[5][6][7]. In VLSI technology, reduction operators, i.e.…”

Section: Introductionmentioning

confidence: 99%

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

Cini

Kurt

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16x16bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on Altera TM Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiplyaccumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.

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Redundant arithmetic, algorithms and implementations

Cited by 32 publications

References 44 publications

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

An alternative carry-save arithmetic for new generation field programmable gate arrays

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

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