A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Pfaff, D.; Abbott, Robert E.; Wang, Xinjie; Moazzeni, Shahaboddin; Mason, R.; Smith, Raleigh

doi:10.1109/jssc.2019.2946134

Cited by 21 publications

(1 citation statement)

References 18 publications

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“…The interface controller layer is the application used to transfer all test data in the USB interface test system. The USB driver is enabled by the developer to support the host software test data, so the USB driver connects to the host software to generate test operations and is built into the processor to complete the communication between the two data bridges and is the bridge for the entire software system [10]. The built-in software layer program consists of a program that works on the ARM core panel and software that works on the FPGA test board and is mainly used to set the parameters of certain test units and to collect and provide test information.…”

Section: Pc Upper Computermentioning

confidence: 99%

Digital integrated circuit test generation algorithm based on neural network technology

2023

Second International Conference on Electronic Information Engineering, Big Data, and Computer Technology (EIBDCT 2023)

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As digital integrated circuit(IC) design techniques and corresponding product manufacturing processes improve, more and more electronic products are moving towards miniaturisation and high concentration, but this is what makes circuit test generation difficult. Since there is a strong link between digital IC test generation and fault diagnosis of digital systems, neural network techniques are applied to fault diagnosis to enable test generation algorithms to accomplish goals such as fault activation and fault propagation. This paper is based on a neural network algorithm to solve circuit fault test sets, generate test vectors and simulate the fault detection process until all fault points have been detected. By comparing the circuit test simulation experiments of the neural network algorithm and the traditional algorithm, it is found that the number of circuit faults increases and the test time of the neural network algorithm is longer than that of the traditional algorithm, but the fault coverage rate is higher than that of the traditional algorithm, indicating that the neural network algorithm can effectively improve the correct fault detection rate although it increases the test time.

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Section: Pc Upper Computermentioning

confidence: 99%

Digital integrated circuit test generation algorithm based on neural network technology

2023

Second International Conference on Electronic Information Engineering, Big Data, and Computer Technology (EIBDCT 2023)

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Exploring the Potential of Dielectric Modulated SOI Junctionless FinFETs for Label-Free Biosensing

Raj,

Sharma

2023

J. Electron. Mater.

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Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art

Yang

Yin

Liu

et al. 2023

Chip

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A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Cited by 21 publications

References 18 publications

Digital integrated circuit test generation algorithm based on neural network technology

Digital integrated circuit test generation algorithm based on neural network technology

Exploring the Potential of Dielectric Modulated SOI Junctionless FinFETs for Label-Free Biosensing

Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art

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