Digital integrated circuit test generation algorithm based on neural network technology

Abstract

As digital integrated circuit(IC) design techniques and corresponding product manufacturing processes improve, more and more electronic products are moving towards miniaturisation and high concentration, but this is what makes circuit test generation difficult. Since there is a strong link between digital IC test generation and fault diagnosis of digital systems, neural network techniques are applied to fault diagnosis to enable test generation algorithms to accomplish goals such as fault activation and fault propagation. This paper is based on a neural network algorithm to solve circuit fault test sets, generate test vectors and simulate the fault detection process until all fault points have been detected. By comparing the circuit test simulation experiments of the neural network algorithm and the traditional algorithm, it is found that the number of circuit faults increases and the test time of the neural network algorithm is longer than that of the traditional algorithm, but the fault coverage rate is higher than that of the traditional algorithm, indicating that the neural network algorithm can effectively improve the correct fault detection rate although it increases the test time.