A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Abstract

In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .

A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

“…With the rapid development of wireless communication systems and measurement instruments, the demands for high-speed and high-resolution analog-to-digital converters (ADCs) are increasing [1]. Among the variety of ADC architectures, such as flash [2,3,4], folding [5,6,7], successive approximation register (SAR) [8,9,10] sigmadelta (Σ∆) [11,12,13] and so on, the pipelined ADC offers a balance between sampling rate and resolution [14,15].…”

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

“…Compared with other architectures, a pipelined ADC is more suitable for highspeed and high-resolution applications like the wideband receiver system [1,2,3]. A SHA-less architecture with an input buffer has been widely employed to design highspeed pipelined ADCs [4,5]. However, the input buffer's dynamic performance usually limits the system's linearity [6,7].…”

“…Implementation of each stages Simplified schematic of the buffer proposed in this paperIEICE Electronics Express, Vol.16, No.11,[1][2][3][4][5] …”

A 12 bit 120 MS/s SHA-less pipeline ADC with capacitor mismatch error calibration

“…A "SHA-less" architecture in which the sample-and-hold circuit is integrated in the first multiplying digital-to-analog converter (MDAC) and without a dedicated amplifier is employed in this paper [3,4]. This architecture can release the difficulty in amplifier design and significantly reducing power consumption.…”