A digital background calibration method correcting nonlinear errors of residue amplifiers in pipelined ADCs is presented. The technique makes use of the proportional scaling feature of linear systems to measure and correct severe nonlinearity errors, and is highly effective once there is a non-zero input to the ADC, regardless of the input distribution. Simulation shows that using the proposed digital calibration, SNDR is improved from 58 dB to 91 dB and SFDR from 68 dB to 104 dB, in a 16 bit prototype pipelined ADC with 1% capacitor mismatches and a residue amplifier having up to 10.3% gain compression in the 1 st pipeline stage.
In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .
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