Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self‐Tracking Comparator Thresholds

A 14b 250MSps Pipelined ADC with Digital Self‐calibration in 0.18µm CMOS Process

“…Many approaches are proposed to resolve the limitations of the resolution and the conversion rate. For example, the digital calibrations used for the capacitor mismatch [2] and the time-interleaving with channel mismatch correction used for the high speed [3] . Capacitor mismatch is one of the key factors which would take obvious effect on the nonlinearity of the switched-capacitor pipelined ADCs [4,5] .…”