A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

Naso, G.; Botticchio, L.; Castelli, Marco; Cerafogli, C.; Cichocki, Mattia; Conenna, P.; D’Alessandro, A.; Santis, Luca De; Cicco, Domenico Di; Francesco, Walter Di; Gallese, M.L.; Gallo, Girolamo; Incarnati, Michele; Lattaro, C.; Macerola, A.; Marotta, G.; Moschiano, Violante; Orlandi, D.; Paolini, F.; Perugini, S.; Pilolli, L.; Pistilli, P.; Rizzo, G.; Rori, F.; Rossini, Massimo; Santin, G.; Sirizotti, E.; Smaniotto, A.; Siciliani, U.; Tiburzi, M.; Meyer, Russ; Goda, Akira; Filipiak, B.; Vali, Tommaso; Helm, Mark; Ghodsi, R.

doi:10.1109/isscc.2013.6487707

Cited by 16 publications

(7 citation statements)

References 3 publications

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“…On the contrary NAND Flash evolution in the last decade has shown an impressive growth rate of a factor or 3Â/year in terms of MB/cm 2 . For NAND Flash this evolution has essentially been achieved by the wide adoption of multi-bit storage, reaching the level of 3 bit/cell for 20 nm technology node [4,5]. Very sophisticated design solutions have been put in place to overcome all problems related to cell to cell electrostatic interference, read disturbs and cycling defects.…”

Section: Evolution Of Mainstream Memorymentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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a b s t r a c tMemory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.

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Section: Evolution Of Mainstream Memorymentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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“…12. This makes the phenomenon dependent on some relevant cell and array parameters, such as: 1) the cell floating-gate height [3]; 2) the floating-gate distance along the bit-line (BL) direction; (corresponding to the array WL half-pitch) and along the WL direction (corresponding to the BL half-pitch) [34]; 3) the depth of the WL penetration between the floating-gates of adjacent cells in the WL direction [35]; and 4) the dielectric constant of the material surrounding the floating-gates [5], [67].…”

Section: A Magnitude Of the Most Relevant Issues For Array Reliabilitymentioning

confidence: 99%

“…1). Thanks to the combined action of a small feature size and a number of bits per cell greater than 1, GBSD close to 1 Gbit/mm 2 were reached by the last 2-D NAND Flash chips [3], [4].…”

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confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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“…This array constitutes a block, whose size is a key element in NAND array organization. Cross-sections of a current planar NAND array are shown on the right of Figure 1: Figure 1a depicts a typical cut along the WL (green = silicon, red = floating gate, magenta = WL, white = silicon oxide), highlighting the shallow trench isolation used to separate the active area of adjacent devices [33] and the planar structure of the cell, without any wrapping of the control gate along the floating gate sidewalls [34]. Figure 1b depicts instead the cross-section along the string direction.…”

Section: Array Architecture and Layoutmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

Cited by 16 publications

References 3 publications

Emerging memories

Emerging memories

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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