a b s t r a c tMemory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.
Heavy metal gettering in silicon devices has been investigated. The best results have been obtained with
POCl3
predeposition followed by annealing at moderate temperature. A model, previously developed for gold, is applied to the description of heavy metal gettering. Once inserted into a standard device process, our gettering step allows us to obtain leakage currents about 100 pA/cm2 and 1 pA/cm for diodes and storage time around 103 sec for capacitors.
A simple model for gettering of gold by phosphorus a t low concentration is proposed. This model assumes that gold is dissolved in single vacancies for intrinsic silicon, and in vacancies paired with phosphorus atoms for doped silicon. Low concentration gettering is directly compatible with MOS technology and allows leakage current in diodes to be reduced of about three orders of magnitude.Nous allons proposer un model pour decrire la capture de l'or par le phosphore. Xotre model est base sur l'hypothhse que l'or est en solution dans les vacances, e t que la capture est due A la formation d'une liaison avec un atom de phosphore. La procedure ici dhcrite pour la capture de l'or est directement compatible avec la technologie MOS.
The NEREID project ("NanoElectronics Roadmap for Europe: Identification and Dissemination") is dedicated to map the future of European Nanoelectronics. NEREID's objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European ecosystem. In addition, it will lead to an early benchmark/identification of promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, and an identification of bottlenecks all along the innovation (value) chain. Considering applications like Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing the NEREID roadmap is about Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview on the roadmap's structure and content.
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