A 128f/sub s/ multi-bit ΣΔ CMOS audio DAC with real-time DEM and 115dB SFDR

Tuijl, Ed van; Homberg, J. van den; Reefman, D.; Bastiaansen, Corné; Dussen, Leon van der

doi:10.1109/isscc.2004.1332747

Cited by 6 publications

(4 citation statements)

References 4 publications

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“…This limit is more stringent than that of any of the previously reported high-end DACs [1][2][3]. High performance and low power are enabled in the present design by using both architectural-and circuit-level considerations.…”

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confidence: 91%

“…27.7.6b compares this architecture with recently published chips reporting comparable SNR. The chip has a power consumption of 21.5mW/channel and consumes 3.5 times less power as compared to previously reported high-end DACs [1][2][3] …”

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confidence: 96%

“…Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1][2][3]. This paper presents a continuous time (CT) area-optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/channel.…”

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confidence: 99%

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A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Bandyopadhyay

Determan

Kim

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low power consumption such that the system can be housed in a small low-cost plastic package. Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1][2][3]. This paper presents a continuous time (CT) area-optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/channel. This performance is achieved by using a new 3-level rotational data shuffling scheme which achieves small area and low digital activity at low signal level, and by applying low-power low-noise analog techniques.Assuming a thermal resistance of 42.3°C/W (typical low-cost LQFP) and a maximum junction temperature of 150°C, a 16 channel DAC would need to have a power consumption of less than 36.9mW/channel for an operational temperature of 125°C. This limit is more stringent than that of any of the previously reported high-end DACs [1-3]. High performance and low power are enabled in the present design by using both architectural-and circuit-level considerations. The first architecture-level consideration is choosing a CT approach so that the analog section of the DAC is less prone to pick up on-chip digital noise. Second, a 2 nd -order 8b modulator is used to reduce clock jitter requirements and to achieve low out-of-band noise. Third, a 3-level rotational dynamic element matching (DEM) scheme is introduced which achieves better SNR performance and lower power consumption than that of previously presented work [4]. Fourth, a signed-magnitude approach is taken at the boundary between the digital and the analog domains such that combined with the 3-level rotational DEM technique would ensure the digital activities at the boundary are proportional to the input signal amplitude which reduces digital coupling effects at low input levels. This approach would also reduce the operational power. At the circuit level the key considerations are the power, noise, and area tradeoffs of the DAC output stage, design of the 3-level current sources (I-DACs) for reduced elementto-element mismatch, and of low-noise voltage reference generators. Figure 27.7.1 shows the block diagram of one channel of the DAC. Digital audio is received at the input by a serial audio interface capable of receiving all standard audio formats. The signal is then passed to a 4× interpolation filter that uses canonical signed-digit arithmetic for low power consumption. The filter also performs volume control and de-emphasis functions. The filter engine output is then further interpolated to 128× via a linear interpolation, and is then presented to the 2 nd -order 8b modulator. For area and power considerations a noise-shaped segmentation technique is used, to split the 8b modulator data into a 4b word with a weight of 16×, and a pair of 3b words with weights of 4× and 1×, respectively. The gain errors between the weighted segments are 1...

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confidence: 91%

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confidence: 96%

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A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Bandyopadhyay

Determan

Kim

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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“…1). The main path is based on [4], containing a 128x oversampled 5-bit 3 rd order noise shaper, thermometer decoder and Real-Time DEM algorithm followed by a current DAC. Since the digital noise shaper generates negligible in-band noise products, the error signal of the noise shaper is practically equal to the OBN.…”

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confidence: 99%

15.3 A 115dB-DR audio DAC with −61dBFS out-of-band noise

Westerveld

Schinkel²,

Tuijl

2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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Out-of-band noise (OBN) is troublesome in analog circuits that process the output of a noise-shaping audio DAC. It causes slewing in amplifiers and aliasing in sampling circuits like ADCs and class-D amplifiers. Non-linearity in these circuits also causes cross-modulation of the OBN into the audio band. These mechanisms lead to a higher noise level and more distortion in the audio band. OBN also leads to interference in the LF and MF band, compromising e.g. AM radio reception. To sufficiently avoid these problems, it is desired to reduce OBN power to below -60dBFS. An active low-pass filter after the DAC output can reduce the OBN power to acceptable low levels, but this solution is expensive in terms of power consumption and chip area. A FIR-DAC[1] approach implements a one-bit PWM modulator, followed by a semi-digital lowpass FIR reconstruction filter. It achieves high-end audio performance with sufficiently low OBN, but the FIR structure costs area, adds latency, and (like an analog low-pass filter) inherently limits the maximum output signal frequency. Multi-bit noise shapers employ smaller quantization steps and therefore output lower OBN. The cascaded modulator architecture[2,3] can directly be followed by an onchip amplifier without low-pass filtering. However, with only 330 quantization levels, it still cannot achieve the desired -60dBFS OBN without additional filtering. Moreover, this approach requires complex dynamic element matching (DEM) and inter-symbol interference (ISI) shaping mechanisms.We present an approach that reduces OBN to below -60dBFS with minimal increase in power and area consumption. It consists of two paths ( fig. 1). The main path is based on [4], containing a 128x oversampled 5-bit 3 rd order noise shaper, thermometer decoder and Real-Time DEM algorithm followed by a current DAC. Since the digital noise shaper generates negligible in-band noise products, the error signal of the noise shaper is practically equal to the OBN. This error signal is integrated (as part of the loop filter), quantized and fed to a correction path with a differentiating DAC (DIFF-DAC). This DAC inverts the integration action, obtaining unity signal transfer. The output currents of both paths are subtracted, reducing OBN significantly. Quantization noise of the correction path is shaped because the error signal is differentiated after quantization. Depending on the shape of the noise transfer function of the main DAC, the DIFF-DAC needs an overrange in order to accommodate the increased signal swing caused by the integration action. Still, area and power cost is minimal because the range of the DIFF-DAC is still only a fraction of the main DAC range.The DIFF-DAC is a semi-digital FIR-DAC with a 1-z A demonstrator chip was designed and manufactured in a 180nm CMOS process. The interpolation filters and the noise shaper were implemented in an FPGA for flexibility. The digital part of the chip contains the 5-bit thermometer decoder, the Real-Time DEM algorithm and the logic circuitry for the DIFF-DAC. To obtain ...

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