A 1024 Pin Universal Interconnect Array With Routing Architecture

Guo, Rongbin; Nguyen, Hung N.; Srinivasan, Arvind; Verheyen, H.; Cai, Hong; Law, S.; Mohsen, A.M.

doi:10.1109/cicc.1992.591112

Cited by 15 publications

(8 citation statements)

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“…A logic circuit is implemented in an FPGA by partitioning logic into individual logic modules and then interconnecting the modules by programming switches. A large circuit that cannot be accommodated into a single FPGA is divided into several parts; each part is realized by an FPGA, and these FPGAs are then interconnected by a field-programmable interconnect chip (FPIC) [Actel Corp. 1992;Aptix, Inc. 1992;Guo et al 1992]. The routing architecture of an FPIC is similar to that of a symmetric-array-based FPGA, whereas the logic modules are replaced by pins (see Figure 3).…”

Section: Introductionmentioning

confidence: 99%

Analysis of FPGA/FPIC switch modules

Chang

Zhu²,

et al. 2003

ACM Trans. Des. Autom. Electron. Syst.

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Switch modules are the most important component of the routing resources in FPGAs/FPICs. Previous works have shown that switch modules with higher routability result in better area performance for practical applications. We consider in this paper an FPGA/FPIC switch-module analysis problem: the inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. As a fundamental problem for the analysis of switch modules, this problem is applicable to the design and routability evaluation of FPGA/FPIC switch modules and FPGA/FPIC routing. We present a network-flow-based approximation algorithm for this problem. Based on mathematical analyses, we show that this algorithm has provably good performance with the bounds 5 and 5/4 away from the optima for two types of switch modules, respectively. Extensive experiments show that this algorithm is highly accurate and runs very efficiently.

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Section: Introductionmentioning

confidence: 99%

Analysis of FPGA/FPIC switch modules

Chang

Zhu²,

et al. 2003

ACM Trans. Des. Autom. Electron. Syst.

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“…It has higher integration than the programmable logic device (PLD) and is extensively used in the implementation of digital logic. To implement circuits that cannot be fitted in a single FPGA, the fieldprogrammable interconnect chip (FPIC) was introduced [1], [9]. In such cases, large circuits are divided into several parts, and each part is implemented in an FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…In such a complete routing, the number of tracks in each channel approaches the lower bound asymptotically. Using our class of routing structures, we can also model the routing structure in FPIC chips proposed in [1] and [9].…”

Section: Introductionmentioning

confidence: 99%

Routing for symmetric FPGAs and FPICs

Sun¹,

Wang²,

Wong³

et al. 1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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where he is responsible for developing fitting algorithms for Altera's complex programmable logic devices involving logic synthesis, technology mapping, partitioning, and place-and-route. His areas of research interest are algorithmic aspects of computer aided design of integrated circuits, combinatorial optimization, and design and analysis of algorithms. degree (first class honors) in mathematics from the University of Hong Kong, Hong Kong, in 1965, and the M.A.

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“…The use of FPGAs for routing results in low FPGA utilization and poor performance. To improve FPGA utilization and performance, newer generations of emulation machines use a combination of FPGAs and dedicated routing chips interconnected via a xed wiring network [2]. Inter-chip routing is done using the routing chips and the xed wires.…”

Section: Introductionmentioning

confidence: 99%

Placement and routing for a field programmable multi-chip module

Lan

Ziv

Gamal

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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| Placemen t and routing heuristics for a Field Programmable Multi-Chip Module (FPMCM) are presented. The placement is done in three phases; partitioning, chip assignment and iterative improvement. The routing is done in two phases; global routing followed by detailed routing. Detailed routing involves new channel routing problems denoted by Exact Segmented Channel Routing (ESCR) and K-ESCR. A very fast K-ESCR heuristic is described. Experimental results show that the placement heuristic achieves high gate utilization, and that the K-ESCR heuristic performs surprisingly well over wide range of channel sizes.

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A 1024 Pin Universal Interconnect Array With Routing Architecture

Cited by 15 publications

References 0 publications

Analysis of FPGA/FPIC switch modules

Analysis of FPGA/FPIC switch modules

Routing for symmetric FPGAs and FPICs

Placement and routing for a field programmable multi-chip module

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